PCIe/CXL Deep Dive · All levels

Coherency and Memory Expansion

Host-device coherency, HDM windows, cacheline ownership flows, and fabric-attached memory integration patterns.

Section goal

Host-device coherency, HDM windows, cacheline ownership flows, and fabric-attached memory integration patterns.

This section trains how to reason from symptoms to PCIe/CXL mechanism, then close with owner accountability, reliability gates, and release-safe decisions.

How to study this section

Start with each topic hub and draw the mechanism path.
Use reports and debug pages to prove causality before tuning.
Practice worked examples and interview drills with explicit evidence chains.
Close each topic with checklist and silicon impact pages.

Topics

host-device-coherency/ - Host-Device Coherency Contracts
hdmm-and-memory-windows/ - HDMM and Host-Managed Device Memory Windows
cacheline-ownership-flows/ - Cacheline Ownership and Transition Flows
fabric-attached-memory/ - Fabric-Attached Memory System Design

PCIe/CXL deep dive

Memory expansion and coherency require HDM windows, ownership discipline, and NUMA-aware software policies.

Concept diagram

diagram

COHERENCY + HDM

CPU caches <-> CXL.cache <-> device memory (CXL.mem/HDM)

Metric graph

diagram

EXPANSION BOTTLENECK SHARE

remote latency      ██████
ownership retry     ████
interleave skew     ███

Reports and artifacts

HDM decode table
ownership transition trace
NUMA distance profile
RAS region policy

Mini case study

Fabric-attached memory increased capacity but p99 regressed until page placement respected NUMA distance.

Debug branches

Map HDM windows and interleave groups
Run ownership litmus under contention
Correlate RAS events with region offline policy

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this PCIe/CXL topic is closed under real traffic?

Practice this lesson

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