PCIe/CXL Deep Dive · All levels

PCIe/CXL Deep Dive Cheatsheet

Dense reference for PCIe/CXL bottleneck isolation, timing-aware debug, and closure-ready review decisions.

Debug order

diagram

WORKLOAD -> FIRST FAILING TRANSITION -> MECHANISM -> ARTIFACT -> OWNER -> DECISION

LINK: LTSSM stability vs Recovery retrain loops
CREDITS: posted/NP/completion pool exhaustion
ORDERING: relaxed vs strong paths and fence latency
PHY: EQ preset margin and lane deskew under corner drift
RAS: AER CE/UE, poison handling, surprise-down recovery

Questions before proposing a fix

Which traffic slice fails first and how reproducible is it?
Which command/state transition loses first under fixed tags?
Which artifact proves mechanism causality?
Who owns the smallest reversible fix?
What full-matrix validation and rollback rules close risk?

Practice this lesson