Equalization Phases and Preset Selection

What this topic teaches

Equalization Phases and Preset Selection turns PCIe/CXL theory into production-grade review decisions. Gen3+ links run equalization phases to tune transmitter presets and receiver CTLE/DFE settings. Each phase has timeout and coefficient feedback rules; marginal channels fail only at higher data rates or temperature corners.

The main objective is to identify where the first loss starts in the memory service path, prove it with reproducible traces, and close with the smallest owner-controlled fix.

Senior PCIe/CXL work is less about isolated register tuning and more about cross-layer causality: traffic shape, TLP legality, credit accounting, LTSSM stability, PHY margin, and field reliability must agree before signoff.

Senior-engineer framing question

When EQ phase retry count, preset convergence time, and post-EQ BER regresses, can you prove whether the first failure is locality collapse, timing-window pressure, scheduler fairness loss, lane-margin drift, or reliability policy overhead?

PCIe/CXL PROTOCOL STACK - Equalization Phases and Preset Selection

[Application / Driver]
        |
        v
[Transaction Layer]  TLP headers, routing, ordering, completions
        |
        v
[Data Link Layer]    seq/ack, LCRC, replay buffer
        |
        v
[Physical Layer]     encoding, scrambling, LTSSM, lanes
        |
        v
[Link Partner]

Focus: link physical state changes to service-level latency and bandwidth outcomes
Metric tracked: EQ phase retry count, preset convergence time, and post-EQ BER

Architecture and timing visuals

Draw the mechanism before tuning knobs. These visuals are optimized for design reviews, bring-up triage, and interview whiteboards.

Detect to L0 progression (Equalization Phases)

LTSSM PROGRESSION

Detect -> Polling -> Configuration -> L0
   |          |            |
 refclk    TS1/TS2      link# + lane map

Stalls before L0 indicate PHY/SI or reset sequencing issues.

Equalization phases (Equalization Phases)

EQ PHASE FLOW (Gen3+)

Phase0 -> Phase1 -> Phase2 -> Phase3
  |         |          |          |
preset   TX tune    RX tune   final margin

Timeouts in Phase3 often correlate with retimer or cable loss.

Recovery loop (Equalization Phases)

RECOVERY PATH

L0 --error--> Recovery --success--> L0
                 |
                 +--fail--> Detect (full retrain)

Correlate Recovery with DL replay and service latency spikes.

Array hierarchy context

PCIe TOPOLOGY MAP - Equalization Phases and Preset Selection

[Root Complex]
    |
    +-- Root Port 0 ---- [Switch] ---- [Endpoint A]
    |                      |
    |                      +---- [Endpoint B]
    +-- Root Port 1 ---- [CXL Type 3 Expander]

BDF routing + bridge windows + HDM decode define reachability.

Command timing context

LTSSM TIMELINE - Equalization Phases and Preset Selection

time --->  t0      t1       t2        t3       t4
state      Detect  Polling  Config    L0       Recovery
ordered    -       TS1      TS2       TLP/DLLP TS1/TS2
service    down    train    align     active   retrain

Key checks:
- Detect -> Polling timeout
- Config completion before L0
- Recovery trigger correlation with errors

Controller queue context

CREDIT FLOW VIEW - Equalization Phases and Preset Selection

VC0 posted credits:     [####------] 4/10 available
VC0 non-posted credits: [######----] 6/10 available
VC0 completion credits: [###-------] 3/10 available

Stall signature:
- posted credit exhaustion -> write TLP backpressure
- completion credit exhaustion -> read latency cliff

Ownership layers

OWNERSHIP LAYERS - Equalization Phases and Preset Selection

layer              owner
-----------------  ----------------
protocol/RTL       PHY owner
PHY/SI             PHY + SI/PI owner
firmware/OS        FW + driver owner
validation         compliance + post-silicon

Evidence to collect before changing knobs

Fast closure comes from complete evidence packets, not from isolated counter wins. Every recommendation should carry a metric, artifact, owner, and rollback-safe validation plan.

• Primary metric: EQ phase retry count, preset convergence time, and post-EQ BER.

• Primary artifact: EQ coefficient log, preset matrix, and margin sweep report.

• Owners to include: PHY owner, SI/PI owner, bring-up engineer, validation owner.

• One reproducible failing traffic slice plus one stable comparator capture.

• One command legality timeline that isolates first failing transition.

• One margin or reliability packet when PHY or RAS behavior is implicated.

Bandwidth-latency operating lens

BANDWIDTH/LATENCY CURVE - Equalization Phases and Preset Selection

throughput
    ^
    |     ****  (peak Gen5 x16)
    |   **    **
    |  *        *  <- tail latency inflation
    +----------------> offered load

Metric: EQ phase retry count, preset convergence time, and post-EQ BER

Root-cause decision tree

ROOT CAUSE TREE - Equalization Phases and Preset Selection

symptom: EQ phase retry count, preset convergence time, and post-EQ BER
  |-- LTSSM / PHY margin
  |-- credit / ordering stall
  |-- coherency / HDM config
  |-- RAS / poison handling
  |-- enumeration / resource conflict

Key takeaways

• Prove first failing transition before touching broad tuning policies.

• Tie command-level behavior to application-visible QoS outcomes.

• Close with accountable owner, rollback criteria, and corner validation.

Common pitfalls

• Optimizing average GB/s while p99 latency and fairness degrade.

• Comparing traces without fixed firmware, timing profile, and thermal tags.

• Declaring closure without reliability and retrain robustness checks.

PCIe/CXL deep dive

LTSSM and equalization determine whether high-speed links are stable under corner traffic and retimer paths.

Concept diagram

LTSSM + EQ

Detect -> Polling -> Config -> L0 <-> Recovery

Metric graph

LINK INSTABILITY SOURCES

EQ margin           ██████
retimer FW          ████
SI/cable plant      ███

Reports and artifacts

• LTSSM state log

• EQ coefficient dump

• negotiated speed/width snapshot

• recovery trigger timeline

Mini case study

Gen5 passed cold boot EQ but entered Recovery loops under DMA heat after retimer firmware update.

Debug branches

• Capture ordered sets at failure boundary

• Compare EQ presets across temperature corners

• Bypass retimer to isolate segment faults

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this PCIe/CXL topic is closed under real traffic?

Key takeaways

• Always tie controller and PHY counter shifts to application latency and throughput outcomes.

• Lock firmware timing profile, thermal condition, and DIMM state before comparing PCIe/CXL captures.

Common pitfalls

• Chasing peak bandwidth while ignoring p99 latency and fairness tails.

• Changing timing guardbands without separating SI noise from scheduling issues.

• Declaring closure without reliability gates, fault injection, and regression replay.