PCIe/CXL Deep Dive · All levels

PCIe Transactions and DMA

Memory/I/O/config TLPs, completions, atomics, ordering, and DMA/peer-to-peer patterns across modern PCIe fabrics.

Section goal

Memory/I/O/config TLPs, completions, atomics, ordering, and DMA/peer-to-peer patterns across modern PCIe fabrics.

This section trains how to reason from symptoms to PCIe/CXL mechanism, then close with owner accountability, reliability gates, and release-safe decisions.

How to study this section

Start with each topic hub and draw the mechanism path.
Use reports and debug pages to prove causality before tuning.
Practice worked examples and interview drills with explicit evidence chains.
Close each topic with checklist and silicon impact pages.

Topics

memory-io-config-tlps/ - Memory, I/O, and Configuration TLP Formats
completions-and-tags/ - Completions, Tags, and Split-Transaction Tracking
atomics-and-ordering/ - Atomic Operations and Advanced Ordering
dma-and-peer-to-peer/ - DMA Engines and Peer-to-Peer Transfers

PCIe/CXL deep dive

Transaction patterns (tags, atomics, DMA, P2P) dominate performance and correctness beyond raw link speed.

Concept diagram

diagram

TRANSACTION LIFECYCLE

MemRd -> tag alloc -> completion(s) -> tag free

Metric graph

diagram

TRANSACTION LOSS MIX

tag exhaustion      █████
P2P fallback        ████
atomic retry        ███

Reports and artifacts

TLP type histogram
tag pool timeline
atomic trace
P2P path verification matrix

Mini case study

Tag leaks after split-completion stress stalled non-posted traffic while the link remained in L0.

Debug branches

Track outstanding tags and completion latency
Verify P2P with ACS/IOMMU policy matrix
Run coherency litmus for atomics and ordering attrs

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this PCIe/CXL topic is closed under real traffic?

Practice this lesson

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