Error Handling and RAS

Section goal

AER, poison/ECRC, surprise-down handling, and containment/recovery strategies for PCIe/CXL fabrics.

This section trains how to reason from symptoms to PCIe/CXL mechanism, then close with owner accountability, reliability gates, and release-safe decisions.

How to study this section

1. Start with each topic hub and draw the mechanism path.

2. Use reports and debug pages to prove causality before tuning.

3. Practice worked examples and interview drills with explicit evidence chains.

4. Close each topic with checklist and silicon impact pages.

Topics

1. aer-errors/ - Advanced Error Reporting (AER)

2. poison-and-ecrc/ - Poisoned TLPs and ECRC Protection

3. surprise-down-handling/ - Surprise Down and Link Loss Handling

4. containment-and-recovery/ - Error Containment and Recovery Policies

Related topics

• PCIe/CXL Deep Dive course hub

PCIe/CXL deep dive

RAS closure maps AER, poison, and surprise-down events to bounded containment and recovery actions.

Concept diagram

RAS ESCALATION

detect -> classify -> contain -> recover -> validate

Metric graph

RAS EVENT MIX

correctable trend   ███████
uncorrectable       ██
surprise-down       █

Reports and artifacts

• AER register dump

• poison injection log

• surprise-down timeline

• containment action record

Mini case study

Masked correctable errors accumulated until a surprise-down during peak traffic forced unplanned failover.

Debug branches

• Separate CE trend from UE containment paths

• Validate poison handling end-to-end

• Test surprise-down drain and driver recovery

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this PCIe/CXL topic is closed under real traffic?