PCIe/CXL Deep Dive · All levels
Link Training and LTSSM: Tricky Q&A
Senior interview and review questions for Link Training and LTSSM.
Section Q&A bank
Use these drills after completing all topics in Link Training and LTSSM. Answer with workload context, mechanism proof, artifact, owner, and release decision.
What is the first evidence that a link is stuck in Polling instead of Configuration?
diagram
[INT][PCIE-CXL][LINK-TRAINING-LTSSM]
Q: What is the first evidence that a link is stuck in Polling instead of Configuration?
A:
Repeated TS1 ordered sets without TS2 progression and no lane-to-lane deskew lock. Electrical idle may toggle but link numbers remain unresolved. Compare active lane map against expected width.
FOLLOW-UP TRAP: Declaring PHY failure before checking refclk, reset sequencing, and lane polarity inversion.Why does equalization fail at Gen5 but pass at Gen4 on the same channel?
diagram
[INT][PCIE-CXL][LINK-TRAINING-LTSSM]
Q: Why does equalization fail at Gen5 but pass at Gen4 on the same channel?
A:
Higher data rates need more aggressive equalization and lower BER. Insufficient RX margin, retimer compatibility, or preset table limits appear only at top speed. Gen4 success does not prove Gen5 closure.
FOLLOW-UP TRAP: Signing off at highest passing speed without margin headroom at target corner.How does width negotiation interact with skew calibration?
diagram
[INT][PCIE-CXL][LINK-TRAINING-LTSSM]
Q: How does width negotiation interact with skew calibration?
A:
Deskew trains on active lanes only; losing a lane changes group delay profile and may require re-equalization. Downgrading from x16 to x8 changes routing and bandwidth but must still satisfy per-lane timing.
FOLLOW-UP TRAP: Assuming lane reversal or width change preserves prior EQ settings without retrain.When should firmware force full retrain versus entering Recovery?
diagram
[INT][PCIE-CXL][LINK-TRAINING-LTSSM]
Q: When should firmware force full retrain versus entering Recovery?
A:
Recovery preserves DL state for transient errors; full retrain is needed after fundamental changes like speed cap updates, retimer mode changes, or persistent deskew failure. Forcing the wrong path extends downtime or leaves marginal EQ in place.
FOLLOW-UP TRAP: Always hot-resetting on first CRC spike without classifying transient vs structural failure.Q&A drill guide
diagram
WORKLOAD -> PCIe/CXL SYMPTOM -> TIMING/QUEUE METRIC -> ROOT CAUSE -> FIX -> REGRESSIONSketch while answering
diagram
LTSSM + EQ
Detect -> Polling -> Config -> L0 <-> RecoveryKey takeaways
Always tie controller and PHY counter shifts to application latency and throughput outcomes.
Lock firmware timing profile, thermal condition, and DIMM state before comparing PCIe/CXL captures.
Common pitfalls
Chasing peak bandwidth while ignoring p99 latency and fairness tails.
Changing timing guardbands without separating SI noise from scheduling issues.
Declaring closure without reliability gates, fault injection, and regression replay.