GPU Design · All levels

Branch Divergence & Predication

Warp Scheduling & Control Flow: Divergent control flow serializes paths under lane masks; predication can reduce branch overhead but may execute extra instructions.

What this topic teaches

Branch Divergence & Predication converts GPU architecture concepts into review-ready engineering decisions. Divergent control flow serializes paths under lane masks; predication can reduce branch overhead but may execute extra instructions. The practical goal is to tie counters and traces to a specific mechanism, owner, and closure action.

The senior-engineer question

When divergence rate, reconvergence delay, and branch efficiency shifts, can you prove whether the root cause is SIMT control flow, SM scheduling, memory traffic, interconnect pressure, or graphics stage imbalance?

diagram

SIMT EXECUTION — Branch Divergence & Predication

warp 0 lanes:  0 1 2 3 4 5 6 7 ... 31
active mask :  1 1 1 1 0 0 1 1 ...  1
instruction :  IF branch taken on active lanes

cycle 10: issue warp 0
cycle 11: issue warp 3
cycle 12: warp 0 reconverges

Focus: anchor discussion in lane masks and warp progress
Metric tracked: divergence rate, reconvergence delay, and branch efficiency

Picture the architecture

Begin with an architecture sketch before touching tuning knobs. These diagrams are for design reviews, interview whiteboards, and closure discussions.

Divergence and reconvergence masks

diagram

SIMT EXECUTION — Branch Divergence & Predication

warp 0 lanes:  0 1 2 3 4 5 6 7 ... 31
active mask :  1 1 1 1 0 0 1 1 ...  1
instruction :  IF branch taken on active lanes

cycle 10: issue warp 0
cycle 11: issue warp 3
cycle 12: warp 0 reconverges

Focus: trace active-lane loss across branch paths and reconvergence point
Metric tracked: divergence rate, reconvergence delay, and branch efficiency

Divergence regression triage

diagram

ROOT-CAUSE TREE — Branch Divergence & Predication

divergence rate, reconvergence delay, and branch efficiency regressed
        |
  reproducible on replay?
      /              \
    no                yes
    |                  |
env/test noise    counter triage
                   |
             compute-bound or memory-bound?
                /                  \
             compute            memory/interconnect
             issue stalls       cache/NoC/DRAM stalls

Stop at first failing mechanism, then patch.

SM and datapath context

diagram

SM BLOCK DIAGRAM — Branch Divergence & Predication

        +---------------------------+
        | Warp Schedulers / Dispatch|
        +------------+--------------+
                     |
     +---------------+----------------+
     |  Register File / Operand Cross |
     +--------+---------------+-------+
              |               |
           [ALU/FPU]       [LD/ST]
              |               |
              +-------+-------+
                      |
                L1 / Shared Mem

Focus: front-end to execute dataflow

Memory hierarchy context

diagram

GPU MEMORY HIERARCHY — Branch Divergence & Predication

                [ Registers ]
              latency:   1-2 cycles
                     |
                [ Shared/L1 ]
              latency:  20-40 cycles
                     |
                    [ L2 ]
              latency: 150-250 cycles
                     |
             [ HBM/GDDR VRAM ]
              latency: 300ns+ effective

Optimization lens: capacity vs latency

Scheduler context

diagram

WARP SCHEDULER VIEW — Branch Divergence & Predication

cycle ->      0    1    2    3    4
eligible   [W1,W2,W5] [W2] [W2,W7] [W7] [W3,W7]
issued         W1      W2    W7      W7    W3
stall reason    -    dep wait  -   mem wait  -

Scheduler objective: keep issue slots non-empty.
Focus: eligible warp quality

Ownership layers

diagram

GPU OWNERSHIP LAYERS — Branch Divergence & Predication

artifact area     owner
----------------  ----------------------------
architecture    compiler backend owner
RTL/microarch   SM RTL owner
software/tools  performance engineer

Rule: each metric needs a named owner before signoff.

Evidence to collect

Primary metric: divergence rate, reconvergence delay, and branch efficiency.
Primary artifact: branch mask timeline, reconvergence stack trace, and predication tradeoff report.
Owners to include: compiler backend owner, SM RTL owner, performance engineer.
One reproducible failing workload and one stable comparator workload.
One counter capture that separates compute issue from memory/interconnect pressure.

Roofline lens

diagram

BANDWIDTH ROOFLINE — Branch Divergence & Predication

performance
   ^
   |                compute ceiling
   |               /
   |              /
   |-------------/------------------ memory ceiling
   +------------------------------------------> operational intensity
      memory-bound             compute-bound

Interpretation: identify compute vs memory bound

Coalescing lens

diagram

COALESCING PATTERN — Branch Divergence & Predication

WARP ADDRESSES
lane: 0 1 2 3 4 5 6 7
addr: 0 4 8 C 10 14 18 1C    -> contiguous -> 1 transaction segment

lane: 0 1 2 3 4 5 6 7
addr: 0 40 8 48 10 50 18 58  -> strided/scatter -> many segments

Effect: fewer coalesced segments => better bandwidth efficiency.
Focus: transaction inflation from scatter

Subpages in this topic

Each topic includes mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory deep dive, design space, case study, walkthrough, matrix, software view, and silicon impact.

Key takeaways

Always connect warp behavior to measured counters before proposing fixes.
Treat memory transaction quality as equal priority to compute utilization.
Close decisions with explicit owners and reproducible benchmark evidence.

Common pitfalls

Copying tuning patterns from unrelated workloads or scenes.
Using occupancy as a success metric without stall classification.
Declaring closure without end-to-end frame or kernel validation.

GPU deep dive

Warp scheduling quality determines whether latency hiding survives real control-flow and memory variance.

Concept diagram

diagram

WARP SCHEDULING LOOP

ready warp? -> issue -> dependency wait -> reconverge -> issue

Metric graph

diagram

STALL REASON SHARE

long scoreboard    ███████
divergence replay  █████
barrier wait       ███

Reports and artifacts

eligible warp ratio
stall reason histogram
barrier wait cycles
scheduler fairness report

Mini case study

A barrier-heavy kernel looked occupancy-safe, but warp arrival imbalance turned sync points into dominant stalls.

Debug branches

Compare scheduler policy traces under bursty workloads
Measure reconvergence delay and predication side effects
Quantify barrier idle time before tuning launch size

Senior review question

Ask: which metric and benchmark pairing proves this topic is truly closed in production context?

Key takeaways

Always pair micro-kernel metrics with end-to-end workload impact.
Lock toolchain, driver, and launch metadata before comparing performance results.

Common pitfalls

Optimizing occupancy without checking memory-system saturation.
Comparing profiler captures from different driver or compiler builds.
Declaring wins without reproducible accuracy and performance gates.

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