GPU Design · All levels

Tile-Based Deferred Rendering

Graphics Pipeline Architecture: TBDR bins primitives by tiles and defers shading to maximize local reuse, reducing external memory traffic versus immediate-mode rendering.

What this topic teaches

Tile-Based Deferred Rendering converts GPU architecture concepts into review-ready engineering decisions. TBDR bins primitives by tiles and defers shading to maximize local reuse, reducing external memory traffic versus immediate-mode rendering. The practical goal is to tie counters and traces to a specific mechanism, owner, and closure action.

The senior-engineer question

When on-chip tile reuse, off-chip bandwidth saved, and tile flush frequency shifts, can you prove whether the root cause is SIMT control flow, SM scheduling, memory traffic, interconnect pressure, or graphics stage imbalance?

diagram

SIMT EXECUTION — Tile-Based Deferred Rendering

warp 0 lanes:  0 1 2 3 4 5 6 7 ... 31
active mask :  1 1 1 1 0 0 1 1 ...  1
instruction :  IF branch taken on active lanes

cycle 10: issue warp 0
cycle 11: issue warp 3
cycle 12: warp 0 reconverges

Focus: anchor discussion in lane masks and warp progress
Metric tracked: on-chip tile reuse, off-chip bandwidth saved, and tile flush frequency

Picture the architecture

Begin with an architecture sketch before touching tuning knobs. These diagrams are for design reviews, interview whiteboards, and closure discussions.

TBDR tile locality model

diagram

TILE-BASED DEFERRED RENDERING

bin primitives -> per-tile visibility -> deferred shading -> tile resolve -> external write
       |                 |                    |                  |
   bin memory       depth reuse          on-chip reuse       flush frequency

Goal: maximize on-chip tile reuse before costly external memory resolve.

Tile memory hierarchy interaction

diagram

GPU MEMORY HIERARCHY — Tile-Based Deferred Rendering

                [ Registers ]
              latency:   1-2 cycles
                     |
                [ Shared/L1 ]
              latency:  20-40 cycles
                     |
                    [ L2 ]
              latency: 150-250 cycles
                     |
             [ HBM/GDDR VRAM ]
              latency: 300ns+ effective

Optimization lens: position tile buffers as locality layer that reduces off-chip bandwidth

SM and datapath context

diagram

SM BLOCK DIAGRAM — Tile-Based Deferred Rendering

        +---------------------------+
        | Warp Schedulers / Dispatch|
        +------------+--------------+
                     |
     +---------------+----------------+
     |  Register File / Operand Cross |
     +--------+---------------+-------+
              |               |
           [ALU/FPU]       [LD/ST]
              |               |
              +-------+-------+
                      |
                L1 / Shared Mem

Focus: front-end to execute dataflow

Memory hierarchy context

diagram

GPU MEMORY HIERARCHY — Tile-Based Deferred Rendering

                [ Registers ]
              latency:   1-2 cycles
                     |
                [ Shared/L1 ]
              latency:  20-40 cycles
                     |
                    [ L2 ]
              latency: 150-250 cycles
                     |
             [ HBM/GDDR VRAM ]
              latency: 300ns+ effective

Optimization lens: capacity vs latency

Scheduler context

diagram

WARP SCHEDULER VIEW — Tile-Based Deferred Rendering

cycle ->      0    1    2    3    4
eligible   [W1,W2,W5] [W2] [W2,W7] [W7] [W3,W7]
issued         W1      W2    W7      W7    W3
stall reason    -    dep wait  -   mem wait  -

Scheduler objective: keep issue slots non-empty.
Focus: eligible warp quality

Ownership layers

diagram

GPU OWNERSHIP LAYERS — Tile-Based Deferred Rendering

artifact area     owner
----------------  ----------------------------
architecture    graphics architect
RTL/microarch   memory architect
software/tools  driver team

Rule: each metric needs a named owner before signoff.

Evidence to collect

Primary metric: on-chip tile reuse, off-chip bandwidth saved, and tile flush frequency.
Primary artifact: tile binning trace, tile memory footprint log, and bandwidth delta report.
Owners to include: graphics architect, memory architect, driver team.
One reproducible failing workload and one stable comparator workload.
One counter capture that separates compute issue from memory/interconnect pressure.

Roofline lens

diagram

BANDWIDTH ROOFLINE — Tile-Based Deferred Rendering

performance
   ^
   |                compute ceiling
   |               /
   |              /
   |-------------/------------------ memory ceiling
   +------------------------------------------> operational intensity
      memory-bound             compute-bound

Interpretation: identify compute vs memory bound

Coalescing lens

diagram

COALESCING PATTERN — Tile-Based Deferred Rendering

WARP ADDRESSES
lane: 0 1 2 3 4 5 6 7
addr: 0 4 8 C 10 14 18 1C    -> contiguous -> 1 transaction segment

lane: 0 1 2 3 4 5 6 7
addr: 0 40 8 48 10 50 18 58  -> strided/scatter -> many segments

Effect: fewer coalesced segments => better bandwidth efficiency.
Focus: transaction inflation from scatter

Subpages in this topic

Each topic includes mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory deep dive, design space, case study, walkthrough, matrix, software view, and silicon impact.

Key takeaways

Always connect warp behavior to measured counters before proposing fixes.
Treat memory transaction quality as equal priority to compute utilization.
Close decisions with explicit owners and reproducible benchmark evidence.

Common pitfalls

Copying tuning patterns from unrelated workloads or scenes.
Using occupancy as a success metric without stall classification.
Declaring closure without end-to-end frame or kernel validation.

GPU deep dive

Frame-time stability depends on balancing fixed-function stages with programmable shader pressure.

Concept diagram

diagram

GRAPHICS PIPELINE

vertex -> tessellation -> raster -> fragment -> ROP/blend

Metric graph

diagram

FRAME-TIME PRESSURE

fragment shading load  ████████
raster backpressure    █████
ROP/blend stalls       ████

Reports and artifacts

stage occupancy timeline
early-Z efficiency report
ROP queue depth
overdraw heatmap

Mini case study

Async compute overlapped with heavy fragment scenes and triggered ROP queue buildup, causing p99 frame spikes.

Debug branches

Correlate frame spikes with stage-level queues
Validate early-Z effectiveness under real content
Isolate graphics-compute arbitration conflicts

Senior review question

Ask: which metric and benchmark pairing proves this topic is truly closed in production context?

Key takeaways

Always pair micro-kernel metrics with end-to-end workload impact.
Lock toolchain, driver, and launch metadata before comparing performance results.

Common pitfalls

Optimizing occupancy without checking memory-system saturation.
Comparing profiler captures from different driver or compiler builds.
Declaring wins without reproducible accuracy and performance gates.

Practice this lesson