GPU Design · All levels
Memory Controllers (HBM/GDDR)
Compute Fabric & Memory System: Controller scheduling, bank mapping, and timing policy convert theoretical HBM/GDDR bandwidth into workload-observed throughput.
What this topic teaches
Memory Controllers (HBM/GDDR) converts GPU architecture concepts into review-ready engineering decisions. Controller scheduling, bank mapping, and timing policy convert theoretical HBM/GDDR bandwidth into workload-observed throughput. The practical goal is to tie counters and traces to a specific mechanism, owner, and closure action.
The senior-engineer question
When effective bandwidth, page-hit rate, and controller queue utilization shifts, can you prove whether the root cause is SIMT control flow, SM scheduling, memory traffic, interconnect pressure, or graphics stage imbalance?
SIMT EXECUTION — Memory Controllers (HBM/GDDR)
warp 0 lanes: 0 1 2 3 4 5 6 7 ... 31
active mask : 1 1 1 1 0 0 1 1 ... 1
instruction : IF branch taken on active lanes
cycle 10: issue warp 0
cycle 11: issue warp 3
cycle 12: warp 0 reconverges
Focus: anchor discussion in lane masks and warp progress
Metric tracked: effective bandwidth, page-hit rate, and controller queue utilizationPicture the architecture
Begin with an architecture sketch before touching tuning knobs. These diagrams are for design reviews, interview whiteboards, and closure discussions.
Controller placement in hierarchy
GPU MEMORY HIERARCHY — Memory Controllers (HBM/GDDR)
[ Registers ]
latency: 1-2 cycles
|
[ Shared/L1 ]
latency: 20-40 cycles
|
[ L2 ]
latency: 150-250 cycles
|
[ HBM/GDDR VRAM ]
latency: 300ns+ effective
Optimization lens: connect L2 miss traffic to HBM/GDDR scheduling behaviorBandwidth efficiency roofline
BANDWIDTH ROOFLINE — Memory Controllers (HBM/GDDR)
performance
^
| compute ceiling
| /
| /
|-------------/------------------ memory ceiling
+------------------------------------------> operational intensity
memory-bound compute-bound
Interpretation: distinguish theoretical bus bandwidth from achieved bandwidthSM and datapath context
SM BLOCK DIAGRAM — Memory Controllers (HBM/GDDR)
+---------------------------+
| Warp Schedulers / Dispatch|
+------------+--------------+
|
+---------------+----------------+
| Register File / Operand Cross |
+--------+---------------+-------+
| |
[ALU/FPU] [LD/ST]
| |
+-------+-------+
|
L1 / Shared Mem
Focus: front-end to execute dataflowMemory hierarchy context
GPU MEMORY HIERARCHY — Memory Controllers (HBM/GDDR)
[ Registers ]
latency: 1-2 cycles
|
[ Shared/L1 ]
latency: 20-40 cycles
|
[ L2 ]
latency: 150-250 cycles
|
[ HBM/GDDR VRAM ]
latency: 300ns+ effective
Optimization lens: capacity vs latencyScheduler context
WARP SCHEDULER VIEW — Memory Controllers (HBM/GDDR)
cycle -> 0 1 2 3 4
eligible [W1,W2,W5] [W2] [W2,W7] [W7] [W3,W7]
issued W1 W2 W7 W7 W3
stall reason - dep wait - mem wait -
Scheduler objective: keep issue slots non-empty.
Focus: eligible warp qualityOwnership layers
GPU OWNERSHIP LAYERS — Memory Controllers (HBM/GDDR)
artifact area owner
---------------- ----------------------------
architecture memory controller owner
RTL/microarch memory system lead
software/tools firmware owner
Rule: each metric needs a named owner before signoff.Evidence to collect
Primary metric: effective bandwidth, page-hit rate, and controller queue utilization.
Primary artifact: controller scheduling trace, bank conflict histogram, and bandwidth efficiency stack.
Owners to include: memory controller owner, memory system lead, firmware owner.
One reproducible failing workload and one stable comparator workload.
One counter capture that separates compute issue from memory/interconnect pressure.
Roofline lens
BANDWIDTH ROOFLINE — Memory Controllers (HBM/GDDR)
performance
^
| compute ceiling
| /
| /
|-------------/------------------ memory ceiling
+------------------------------------------> operational intensity
memory-bound compute-bound
Interpretation: identify compute vs memory boundCoalescing lens
COALESCING PATTERN — Memory Controllers (HBM/GDDR)
WARP ADDRESSES
lane: 0 1 2 3 4 5 6 7
addr: 0 4 8 C 10 14 18 1C -> contiguous -> 1 transaction segment
lane: 0 1 2 3 4 5 6 7
addr: 0 40 8 48 10 50 18 58 -> strided/scatter -> many segments
Effect: fewer coalesced segments => better bandwidth efficiency.
Focus: transaction inflation from scatterSubpages in this topic
Each topic includes mechanism, inputs/outputs, reports, debug, worked example, pitfalls, interview, checklist, theory deep dive, design space, case study, walkthrough, matrix, software view, and silicon impact.
Key takeaways
Always connect warp behavior to measured counters before proposing fixes.
Treat memory transaction quality as equal priority to compute utilization.
Close decisions with explicit owners and reproducible benchmark evidence.
Common pitfalls
Copying tuning patterns from unrelated workloads or scenes.
Using occupancy as a success metric without stall classification.
Declaring closure without end-to-end frame or kernel validation.
GPU deep dive
Fabric and memory-controller behavior decides scaling long before peak ALU utilization is reached.
Concept diagram
COMPUTE FABRIC
SM clusters <-> NoC <-> L2 <-> memory controllers <-> HBMMetric graph
SCALING EFFICIENCY
single GPU ███████████ 100%
with heavy NoC ████████
with tuned QoS █████████Reports and artifacts
NoC congestion map
HBM controller queue stats
PCIe/DMA overlap timeline
roofline position report
Mini case study
Crossbar arbitration favored bulk traffic and starved latency-sensitive queues, collapsing tail performance.
Debug branches
Track per-link hotspots, not only aggregate BW
Inspect controller page-hit and queue depth behavior
Validate host-device overlap during peak traffic windows
Senior review question
Ask: which metric and benchmark pairing proves this topic is truly closed in production context?
Key takeaways
Always pair micro-kernel metrics with end-to-end workload impact.
Lock toolchain, driver, and launch metadata before comparing performance results.
Common pitfalls
Optimizing occupancy without checking memory-system saturation.
Comparing profiler captures from different driver or compiler builds.
Declaring wins without reproducible accuracy and performance gates.