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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
    • Sequence Puzzles
    • Implication Puzzles
    • Temporal Corner Puzzles
      • $past Startup History Hole
      • $rose Sampled on Clock Edge
      • $fell Is an Event, Not a Level
      • $stable Repeated Hold Check
      • $past After Reset Release
      • Vector $rose Sampling Trap
    • Assertion Debug Puzzles
    • SVA Assertion Puzzles: Tricky Q&A
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Temporal Corner Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. SVA Assertion Puzzles
  4. Temporal Corner Puzzles
  5. $fell Is an Event, Not a Level
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    VLSI DV Interview PuzzlesAll levels

    $fell Is an Event, Not a Level

    Property intent: when valid falls, idle must be high in that same cycle. Timeline: the test starts at C60 with valid=1; valid=1 through C69, then valid=0 from C70 on. idle=1 at C70 only and idle=0 at every other sampled edge. Evaluate p_fell and p_level.

    Puzzle

    Difficulty: Easy · Puzzle 3 of 6 · Topic: Temporal Corner Puzzles

    Property intent: when valid falls, idle must be high in that same cycle. Timeline: the test starts at C60 with valid=1; valid=1 through C69, then valid=0 from C70 on. idle=1 at C70 only and idle=0 at every other sampled edge. Evaluate p_fell and p_level.

    Code

    design.sv
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    property p_fell;
      @(posedge clk) $fell(valid) |-> idle;
    endproperty
    
    property p_level;
      @(posedge clk) !valid |-> idle;
    endproperty

    Hint

    Count how many sampled edges make each antecedent true.

    Step-by-step solution

    Diagram
    1) $fell(valid) compares valid at this edge with valid at the previous edge. It is true only at C70 (1 at C69, 0 at C70). At C71 and later both samples are 0, so it is false.
    2) p_fell therefore starts exactly one attempt, at C70, where idle is 1. It PASSES.
    3) !valid is a level: it is true at C70, C71, C72 and every later edge. p_level starts an attempt each cycle.
    4) idle is 0 at C71, so p_level FAILS at C71 (and at every later edge).
    5) Same waveform, opposite verdicts: $fell is a one-cycle event, !valid is a state.

    Answer

    Answer: p_fell PASSES (one attempt at C70, idle=1); p_level FAILS from C71 (valid stays low, idle drops).

    How this was checked

    Checked by running the code in Verilator 5; the printed output supports the answer above. $fell is a one-cycle event that passes at C70; !valid is a level and fails as soon as idle drops at C71.

    Why candidates get it wrong

    Candidates read $fell(valid) as 'valid is low' and expect checks in every idle cycle. It fires once, on the edge where the sampled value changes from 1 to 0, so a single idle pulse satisfies it. Use the level form when the requirement is a state, and $fell when it is a transition.

    Interviewer follow-up

    If valid went 1,0,1,0 at C69, C70, C71, C72, how many attempts would p_fell start and where? Model answer: two, at C70 and C72 (each 1 to 0 transition is a fall; the rise at C71 is not). idle must be high at both C70 and C72 or the property fails at the one where it is low.

    Say it out loud

    I would separate event from level. The fell of valid is true only at C70, where idle is high, so that property passes with one attempt. The not valid form is a level, true at C70 and at every later edge, and idle is low at C71, so it fails at C71 and onward. The trap is reading fell as valid is low. I would use fell for a transition requirement and the level form for a state requirement.

    Related topics

    • $rose, $fell, $stable, $changed

    • Back to Temporal Corner Puzzles

    • SVA Assertion Puzzles section

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    See also

    • $past Startup History Hole
    • $past After Reset Release
    • Vector $rose Sampling Trap