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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
    • Sequence Puzzles
      • Exact Delay Then Bounded Hold
      • Goto Repetition With Sparse Events
      • Nonconsecutive Repetition [=2]
      • Sequence and Operator
      • first_match in an Antecedent
      • within Window Length Off-By-One
    • Implication Puzzles
    • Temporal Corner Puzzles
    • Assertion Debug Puzzles
    • SVA Assertion Puzzles: Tricky Q&A
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Sequence Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. SVA Assertion Puzzles
  4. Sequence Puzzles
  5. Sequence and Operator
On this page

    VLSI DV Interview PuzzlesAll levels

    Sequence and Operator

    Property intent: from one start cycle, both sub-sequences must match: req ##1 gnt and req ##2 done. Timeline (all other samples are 0): C40 start=1 req=1, C41 gnt=1, C42 d1. Determine the verdict.

    Puzzle

    Difficulty: Medium · Puzzle 4 of 6 · Topic: Sequence Puzzles

    Property intent: from one start cycle, both sub-sequences must match: req ##1 gnt and req ##2 done. Timeline (all other samples are 0): C40 start=1 req=1, C41 gnt=1, C42 done=1. Determine the verdict.

    Code

    design.sv
    property p_seq_and;
      @(posedge clk) start |-> ((req ##1 gnt) and (req ##2 done));
    endproperty

    Hint

    For sequence and, both sequences share a start but may end at different cycles.

    Step-by-step solution

    Diagram
    1) start triggers and launches both sequence branches at C40.
    2) First branch req ##1 gnt matches (req at C40, gnt at C41).
    3) Second branch req ##2 done matches (req at C40, done at C42).
    4) Both branches match, so the and composition matches, ending at the later end, C42.

    Answer

    Answer: PASS - both sequence branches succeed from the same start cycle, satisfying the sequence and operator.

    How this was checked

    Checked by running the code in Verilator 5; the printed output supports the answer above. Both branches match from C40 (ending C41 and C42), so sequence and passes.

    Why candidates get it wrong

    A common mistake is assuming both branches must end on the same cycle (that is intersect, not and). With and, the composite match ends when the later branch ends (C42 here).

    Interviewer follow-up

    If done moved to C43, which part would fail first and why? Model answer: the second branch (req ##2 done) fails first, at C42, because it needs done two cycles after req and done is still low. The first branch has already matched, but and needs both, so the property FAILS.

    Say it out loud

    I would start both branches at C40. The first, req then gnt, matches at C41, and the second, req then two cycles to done, matches at C42. Both match from the same start, so the and passes, ending at the later branch end, C42. The trap is thinking both branches must end on the same cycle; that is intersect, not and, so I would check which one the spec wants.

    Related topics

    • Composition: and, or, intersect, throughout, within

    • Back to Sequence Puzzles

    • SVA Assertion Puzzles section

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    See also

    • Exact Delay Then Bounded Hold
    • Goto Repetition With Sparse Events
    • within Window Length Off-By-One