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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
    • Sequence Puzzles
      • Exact Delay Then Bounded Hold
      • Goto Repetition With Sparse Events
      • Nonconsecutive Repetition [=2]
      • Sequence and Operator
      • first_match in an Antecedent
      • within Window Length Off-By-One
    • Implication Puzzles
    • Temporal Corner Puzzles
    • Assertion Debug Puzzles
    • SVA Assertion Puzzles: Tricky Q&A
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Sequence Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. SVA Assertion Puzzles
  4. Sequence Puzzles
  5. Exact Delay Then Bounded Hold
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    VLSI DV Interview PuzzlesAll levels

    Exact Delay Then Bounded Hold

    Property intent: after req, gnt must arrive exactly 2 cycles later, then busy must stay high for 2 to 3 consecutive cycles. Timeline (all other samples are 0): C10 req=1, C12 gnt=1, C13 busy=1, C14 busy=0, C15 busy=1. Determine the verdict for the C10 attempt.

    Puzzle

    Difficulty: Medium · Puzzle 1 of 6 · Topic: Sequence Puzzles

    Property intent: after req, gnt must arrive exactly 2 cycles later, then busy must stay high for 2 to 3 consecutive cycles. Timeline (all other samples are 0): C10 req=1, C12 gnt=1, C13 busy=1, C14 busy=0, C15 busy=1. Determine the verdict for the C10 attempt.

    Code

    design.sv
    property p_seq_range;
      @(posedge clk) req |-> ##2 gnt ##1 busy[*2:3];
    endproperty

    Hint

    Check consecutive repetition semantics of [*2:3]. Count busy highs, then count how many are adjacent.

    Step-by-step solution

    Diagram
    1) Antecedent req triggers at C10.
    2) ##2 gnt requires gnt at C12, which is satisfied.
    3) busy[*2:3] starts at C13 and needs two adjacent high samples (C13 and C14) before it may stop, or three (C13, C14, C15).
    4) busy is high at C13 but low at C14, so the run is only one cycle long and the minimum of 2 is not reached. The later high at C15 does not repair it: [*n] never skips cycles.
    5) The attempt fails when the C14 sample is taken.

    Answer

    Answer: FAIL - the attempt from C10 fails at C14: grant timing is correct, but busy has only a one-cycle run (C13), so [*2:3] never reaches its minimum of 2 consecutive cycles.

    How this was checked

    Checked by running the code in Verilator 5; the printed output supports the answer above. The C10 attempt fails at C14: busy is high only one cycle in a row, so [*2:3] never reaches 2.

    Why candidates get it wrong

    The waveform has busy high at C13 and again at C15, so a reading of [*2:3] as 'busy is seen high two or three times' passes it. [*2:3] is consecutive: the C14 low cycle ends the run after one cycle and the C15 high starts a new run that is too late.

    Interviewer follow-up

    If busy were high at C13 and C14 and low at C15, would the same property pass or fail? Model answer: PASS. busy[*2:3] matches the two-cycle run C13..C14 and the match ends at C14. Nothing in the property requires a third high cycle, and the three-cycle alternative simply does not match, which is allowed because [*2:3] is a range.

    Say it out loud

    I would first mark busy per cycle: high at C13, low at C14, high at C15. The grant at C12 is exactly two cycles after req, so that part is fine, but busy[*2:3] needs two consecutive highs starting at C13. The property fails at C14, because the run is only one cycle long and the later high at C15 cannot repair it. The trap is reading the repetition as busy being seen high two or three times; I would next check whether the intent really was consecutive.

    Related topics

    • Repetition: [*], [->], [=]

    • Cycle Delays: ##N and ##[M:N]

    • Back to Sequence Puzzles

    • SVA Assertion Puzzles section

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    See also

    • Nonconsecutive Repetition [=2]
    • Sequence and Operator
    • first_match in an Antecedent