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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
    • Sequence Puzzles
    • Implication Puzzles
    • Temporal Corner Puzzles
    • Assertion Debug Puzzles
      • disable iff Reset Glitch Hides a Lost Grant
      • Multiclock Ack Visibility
      • Weak vs Strong at End of Simulation
      • Overlapping Attempts Share One Grant
      • $rose Consumed During Reset
      • Intersect Requirement in Dual Checks
    • SVA Assertion Puzzles: Tricky Q&A
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Assertion Debug Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. SVA Assertion Puzzles
  4. Assertion Debug Puzzles
  5. Intersect Requirement in Dual Checks
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    VLSI DV Interview PuzzlesAll levels

    Intersect Requirement in Dual Checks

    Property intent: one cycle after a rises, both b and c checks should align in the same endpoint cycle via intersect. Timeline (all other samples are 0): C90 a rises, C91 b=1 c=0, C92 c=1. Determine the verdict.

    Puzzle

    Difficulty: Medium · Puzzle 6 of 6 · Topic: Assertion Debug Puzzles

    Property intent: one cycle after a rises, both b and c checks should align in the same endpoint cycle via intersect. Timeline (all other samples are 0): C90 a rises, C91 b=1 c=0, C92 c=1. Determine the verdict.

    Code

    design.sv
    property p_dual_same_cycle;
      @(posedge clk) $rose(a) |-> ((##1 b) intersect (##1 c));
    endproperty

    Hint

    Both intersect branches must end in the same cycle (here, both at C91).

    Step-by-step solution

    Diagram
    1) $rose(a) at C90 triggers consequent.
    2) ##1 b checks b at C91 and succeeds.
    3) ##1 c checks c at C91 and fails because c=0 there.
    4) intersect therefore fails (reported at C91).

    Answer

    Answer: FAIL - intersect demands simultaneous success at the same endpoint cycle, but c misses at C91.

    How this was checked

    Checked by running the code in Verilator 5; the printed output supports the answer above. intersect needs both branches to succeed with the same end point; c is low at C91, so it fails.

    Why candidates get it wrong

    Engineers may glance at c=1 at C92 and incorrectly assume delayed recovery is acceptable. Both branches are fixed one-cycle delays, so C92 can never be an end point.

    Interviewer follow-up

    What operator would allow b and c to complete on different endpoints from the same start? Model answer: sequence and, for example (##1 b) and (##[1:2] c). Both branches start together and the composite ends at the later end, so b at C91 and c at C92 PASS.

    Say it out loud

    I would check both branches from C90. The first, one cycle then b, succeeds at C91. The second, one cycle then c, checks c at C91 and it is low, so it fails, and the intersect fails at C91. Intersect needs both branches to succeed with the same start and end, and both are fixed one cycle delays, so c at C92 can never count. The trap is assuming a delayed recovery is acceptable. I would check whether the spec wanted and instead of intersect.

    Related topics

    • Composition: and, or, intersect, throughout, within

    • Back to Assertion Debug Puzzles

    • SVA Assertion Puzzles section

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    See also

    • disable iff Reset Glitch Hides a Lost Grant
    • Multiclock Ack Visibility
    • Weak vs Strong at End of Simulation