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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
    • Classic Brain Teasers
    • Probability Puzzles
    • Digital Logic Puzzles
      • Build XOR Using Only 2:1 MUXes
      • One-Cycle Pulse Across Clock Domains
      • Minimum NAND Gates for XOR
      • Overlapping 1011 Sequence Detector
      • Mod-6 Counter Behavior Check
      • Metastability MTBF Improvement Estimate
    • Debugging Riddles
    • Logic & Aptitude Puzzles: Tricky Q&A
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Digital Logic Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Logic & Aptitude Puzzles
  4. Digital Logic Puzzles
  5. Minimum NAND Gates for XOR
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    VLSI DV Interview PuzzlesAll levels

    Minimum NAND Gates for XOR

    Implement XOR using only 2-input NAND gates. What is the minimum number of NAND gates and one valid construction?

    Puzzle

    Difficulty: Medium · Puzzle 3 of 6 · Topic: Digital Logic Puzzles

    Implement XOR using only 2-input NAND gates. What is the minimum number of NAND gates and one valid construction?

    Code

    design.sv
    1
    2
    3
    4
    n1 = ~(A & B);
    n2 = ~(A & n1);
    n3 = ~(B & n1);
    Y  = ~(n2 & n3); // XOR

    Hint

    Use the canonical 4-NAND XOR network.

    Step-by-step solution

    Diagram
    1) Create n1 = NAND(A,B) = ~(A&B).
    2) Create n2 = NAND(A,n1) and n3 = NAND(B,n1).
    3) Final output Y = NAND(n2,n3).
    4) Substituting shows Y = A^B.
    5) This uses 4 NAND gates, which is the known minimum for XOR with 2-input NAND-only logic.

    Answer

    Answer: Minimum is 4 NAND gates.

    How this was checked

    Checked by running a model of the rule in a Python model. A computational check: exhaustive search over every 2-input NAND network shows XOR needs 4 gates (3 are impossible) and XNOR needs 5.

    Why candidates get it wrong

    Claiming 3 NANDs are enough because the shared n1 'looks' like it replaces two gates; with 3 two-input NANDs XOR's truth table cannot be matched. The shared n1 term is what makes 4 possible.

    Interviewer follow-up

    What is the minimum NAND count for XNOR? Model answer: 5 NAND gates. Take the 4-NAND XOR and add a fifth NAND with both inputs tied together as an inverter on the output.

    Say it out loud

    I build the shared term first: n1 is the NAND of A and B. Then n2 is the NAND of A and n1, n3 is the NAND of B and n1, and the output is the NAND of n2 and n3, which works out to A XOR B. That is four NAND gates, which is the known minimum for XOR with two-input NANDs. The trap is claiming three are enough; the shared n1 term is what makes four possible, but you cannot do it with three.

    Related topics

    • Algebra Before Gates

    • Back to Digital Logic Puzzles

    • Logic & Aptitude Puzzles section

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    See also

    • Build XOR Using Only 2:1 MUXes
    • Mod-6 Counter Behavior Check
    • Metastability MTBF Improvement Estimate