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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
    • Classic Brain Teasers
    • Probability Puzzles
    • Digital Logic Puzzles
      • Build XOR Using Only 2:1 MUXes
      • One-Cycle Pulse Across Clock Domains
      • Minimum NAND Gates for XOR
      • Overlapping 1011 Sequence Detector
      • Mod-6 Counter Behavior Check
      • Metastability MTBF Improvement Estimate
    • Debugging Riddles
    • Logic & Aptitude Puzzles: Tricky Q&A
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Digital Logic Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Logic & Aptitude Puzzles
  4. Digital Logic Puzzles
  5. Build XOR Using Only 2:1 MUXes
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    VLSI DV Interview PuzzlesAll levels

    Build XOR Using Only 2:1 MUXes

    Construct Y = A ^ B using only 2:1 multiplexers and constants 0/1. Give one concrete implementation.

    Puzzle

    Difficulty: Easy · Puzzle 1 of 6 · Topic: Digital Logic Puzzles

    Construct Y = A ^ B using only 2:1 multiplexers and constants 0/1. Give one concrete implementation.

    Code

    mux_xor.sv
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    module mux_xor(input logic A, B, output logic Y);
      logic nB;
      // MUX form: Z = S ? D1 : D0
      assign nB = B ? 1'b0 : 1'b1;      // ~B
      assign Y  = A ? nB   : B;         // A?~B:B = A^B
    endmodule

    Hint

    Use one MUX to create ~B, then select between B and ~B using A.

    Step-by-step solution

    Diagram
    1) Recall 2:1 MUX equation: Z = S?D1:D0.
    2) Invert B by setting S=B, D1=0, D0=1 => nB = ~B (the same one-MUX trick gives NOT for any signal).
    3) Build XOR with S=A, D1=nB, D0=B => Y = A?~B:B.
    4) Verify truth table: A=0 => Y=B; A=1 => Y=~B, which equals A^B.
    5) Why not one MUX: with S=A the data inputs would need to be ~B and B, but only A, B, 0, 1 are available (and S=B is symmetric), so no single MUX is XOR. The minimum is 2.
    6) Side result: with constants only, AND is S=A,D1=B,D0=0 and OR is S=A,D1=1,D0=B, one MUX each.

    Answer

    Answer: Two MUXes suffice: one for ~B and one for A-select between B and ~B.

    How this was checked

    Checked by running a model of the rule in Icarus Verilog 13 and a Python model. The shown two-MUX module simulated in Icarus: it matches A^B on all four input pairs, and swapping the data inputs of the second MUX gives XNOR. A computational check: from A, B, 0, 1 no single MUX makes XOR, but two MUXes do; one MUX also gives AND and OR as stated.

    Why candidates get it wrong

    Hunting for a one-MUX XOR. XOR needs both B and ~B as data inputs, and the only way to get ~B is another MUX with constants 0 and 1.

    Interviewer follow-up

    Can you build XNOR with same structure and same MUX count? Model answer: yes, 2 MUXes again. Swap the data inputs of the second MUX: Y = A ? B : nB (A=1 gives B, A=0 gives ~B), which is ~(A^B).

    Say it out loud

    A two-to-one mux with constant inputs makes an inverter, so with select B, data one at zero and data zero at one I get not B in one mux. Then a second mux with select A, picking not B when A is one and B when A is zero, gives A XOR B. So two muxes are enough. One mux cannot do it because XOR needs both B and not B as data inputs, and not B itself costs a mux. The trap is hunting for a single-mux XOR.

    Related topics

    • Mux Theory and Design Patterns

    • Algebra Before Gates

    • Back to Digital Logic Puzzles

    • Logic & Aptitude Puzzles section

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    See also

    • Minimum NAND Gates for XOR
    • Overlapping 1011 Sequence Detector
    • Mod-6 Counter Behavior Check