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Course contents

  • How to Use This Puzzle Bank
  • SystemVerilog Language Puzzles25
  • Difficulty Guide
  • Full Topic Map
  • Interview-Day Tips
  • Study Route: One Week Before the Interview
  • Study Route: Two Weeks
  • Study Route: Four Weeks (Full Course)4
  • OOP & Testbench Puzzles25
  • Concurrency & Timing Puzzles25
  • Randomization & Constraint Puzzles25
  • SVA Assertion Puzzles25
  • Functional Coverage Puzzles25
  • Logic & Aptitude Puzzles25
    • Classic Brain Teasers
    • Probability Puzzles
    • Digital Logic Puzzles
      • Build XOR Using Only 2:1 MUXes
      • One-Cycle Pulse Across Clock Domains
      • Minimum NAND Gates for XOR
      • Overlapping 1011 Sequence Detector
      • Mod-6 Counter Behavior Check
      • Metastability MTBF Improvement Estimate
    • Debugging Riddles
    • Logic & Aptitude Puzzles: Tricky Q&A
  • Scenario & Debug Puzzles25
  • UVM Testbench Puzzles25
  • Clock, Reset & CDC Puzzles25
  • Bus and Interface Protocol Puzzles25
  • Interview Prep: Puzzle Rounds7
  • DV Puzzle Cheatsheet
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←Digital Logic Puzzles
  1. Topics
  2. DV Interview Puzzles
  3. Logic & Aptitude Puzzles
  4. Digital Logic Puzzles
  5. Metastability MTBF Improvement Estimate
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    VLSI DV Interview PuzzlesAll levels

    Metastability MTBF Improvement Estimate

    A synchronizer MTBF is modeled as MTBF proportional to exp(Tresolve/tau). If adding one extra sync flop increases settling time by 2 ns and tau=50 ps, by what factor does MTBF improve?

    Puzzle

    Difficulty: Medium · Puzzle 6 of 6 · Topic: Digital Logic Puzzles

    A synchronizer MTBF is modeled as MTBF proportional to exp(Tresolve/tau). If adding one extra sync flop increases settling time by 2 ns and tau=50 ps, by what factor does MTBF improve?

    Hint

    Compute exp(deltaT/tau) using ratio 2 ns / 50 ps.

    Step-by-step solution

    Diagram
    1) MTBF ratio = exp((Tnew - Told)/tau) = exp(2 ns / 50 ps).
    2) Convert units: 2 ns = 2000 ps.
    3) Exponent = 2000/50 = 40.
    4) Ratio = e^40 approx 2.35 x 10^17.
    5) So one extra stage can massively improve reliability when timing budget allows.
    6) Caveat: the extra stage only buys the resolution time left after clk-to-q and setup of the next flop, so in a real design the gain is e^((T_clk - t_cq - t_setup)/tau) per stage, and a 2 ns gain assumes a slow clock (at 1 GHz a stage buys well under 1 ns).

    Answer

    Answer: MTBF improves by e^40, approximately 2.35e17 times.

    How this was checked

    Checked by running a model of the rule in a Python model. A computational check: exp(2 ns / 50 ps) = exp(40) = 2.35e17.

    Why candidates get it wrong

    Expecting a fixed additive gain per extra stage (like +1 year); the exponent adds, so MTBF multiplies. The opposite mistake is quoting e^40 for a fast clock without subtracting clk-to-q and setup.

    Interviewer follow-up

    Why does this argument not guarantee safe transfer of one-cycle pulses? Model answer: MTBF only measures the chance that a sampled value resolves too late. A pulse shorter than the destination period can fall between two destination edges and never be sampled. Use a toggle or handshake (see the clock-domain pulse puzzle).

    Say it out loud

    The ratio of the two MTBFs is e to the power of the extra resolution time over tau. The extra stage adds 2 nanoseconds, which is 2000 picoseconds, and tau is 50 picoseconds, so the exponent is 40. The improvement is e to the 40, about 2.35 times ten to the 17. The trap is expecting an additive gain, but the exponent adds so MTBF multiplies. Also, in a real design the gain is the clock period minus clock-to-q and setup, so a 2 nanosecond gain assumes a slow clock.

    Related topics

    • MTBF & Synchronizer Math

    • Back to Digital Logic Puzzles

    • Logic & Aptitude Puzzles section

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    See also

    • Build XOR Using Only 2:1 MUXes
    • One-Cycle Pulse Across Clock Domains
    • Minimum NAND Gates for XOR