A logic gate network is a Boolean equation drawn as hardware. Write the equation first, and the gates, the cost estimate, and the test all follow.
Starting from gates usually ends with a design that cannot be explained.
Function | Symbol in equations | Verilog bitwise | Output is 1 when… |
|---|---|---|---|
NOT | a′ or ¬a |
| a is 0 |
AND | a·b |
| both inputs are 1 |
OR | a+b |
| at least one input is 1 |
XOR | a⊕b |
| the inputs differ |
NAND | (a·b)′ |
| not both inputs are 1 |
NOR | (a+b)′ |
| both inputs are 0 |
XNOR | (a⊕b)′ |
| the inputs are equal |
In equations, “+” means OR and “·” (or juxtaposition) means AND. In Verilog + is arithmetic addition.
Mixing the two up is a classic confusion when moving from a textbook to code.
The Verilog bitwise operators &, |, ^, and ~ map one-to-one onto AND, OR, XOR, and NOT.
The most direct way from truth table to equation is sum of products (SOP). For every row where the output is 1, write an AND term (a minterm) true only for that row, then OR the terms.
Take a 3-input majority function. The output is 1 when at least two of three inputs are 1.
a | b | c | y | minterm |
|---|---|---|---|---|
0 | 0 | 0 | 0 | |
0 | 0 | 1 | 0 | |
0 | 1 | 0 | 0 | |
0 | 1 | 1 | 1 | a′·b·c |
1 | 0 | 0 | 0 | |
1 | 0 | 1 | 1 | a·b′·c |
1 | 1 | 0 | 1 | a·b·c′ |
1 | 1 | 1 | 1 | a·b·c |
Four minterms give the raw SOP y = a′bc + ab′c + abc′ + abc. A little algebra (next lesson) collapses it to y = ab + bc + ac, which reads “any two of the three”.
module majority3 (
input wire a, b, c,
output wire y
);
// y = ab + bc + ac : true when at least two inputs are 1
assign y = (a & b) | (b & c) | (a & c);
endmoduleTwo numbers describe a first-order implementation cost, long before a tool runs:
Literals — the total count of variable appearances (ab + bc + ac has 6). More literals generally means more transistors, so more area.
Levels — the longest chain of gates from an input to the output. More levels means more delay.
The raw SOP above has 12 literals; the simplified form has 6. Both are two levels deep: same function, half the literal count. That comparison assumes true and complemented inputs are both available and ignores fan-in limits. Mapped gate cost depends on the library.
Three-input majority has 4 minterms (011, 101, 110, 111). For “at least 3 of 4” there are C(4,3) + C(4,4) = 4 + 1 = 5 minterms.