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Course contents

  • Start Here5
  • SystemVerilog Language Foundations28
  • Object-Oriented SystemVerilog for Verification30
  • Constraint Randomization — Interview-Critical Deep Dive39
  • SystemVerilog Assertions — Interview-Critical Deep Dive41
  • Functional Coverage in SystemVerilog25
  • Testbench Architecture in SystemVerilog24
    • Testbench Anatomy & Layering
      • The Layered Testbench
      • The Static Harness and Environment
      • Tests as Classes
      • Complete Mini Testbench
    • Stimulus: Generators, Transactions & Drivers
    • Monitors, Scoreboards & Reference Models
    • Self-Checking Tests & Regression
    • From Hand-Built TB to UVM
  • Advanced Language & Integration26
  • Senior & Interview Preparation23
  • Principal-Level Verification34
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←Testbench Architecture in SystemVerilog
  1. Topics
  2. SystemVerilog
  3. Testbench Architecture in SystemVerilog
  4. Testbench Anatomy & Layering

Part 6 of 9Part 6 of 9/Testbench ArchitectureIntermediate

Testbench Anatomy & Layering

How a layered testbench is organized, from the static harness to tests and a complete example.

  • 4topics
  • 4lessons

A class-based testbench has two worlds. The static module world holds clocks, reset, interfaces and the DUT, and the dynamic class world holds transactions, drivers, monitors and tests, reaching pins only through virtual interface handles.

Diagram
TB ANATOMY — topic map

  TEST LAYER          base_test, smoke, stress, error      (lesson 3)
       | builds
  ENVIRONMENT         env: gen + drv + mon + scb + wiring  (lesson 2)
       | runs inside
  STATIC HARNESS      tb_top: clk, rst, interface, DUT     (lesson 2)
       | scheduling semantics
  program vs module   folded into lesson 2 as a closing section

  All layers stacked:  THE LAYERED TESTBENCH               (lesson 1)
  All layers together: COMPLETE MINI TESTBENCH             (lesson 4)

Lesson

What it covers

Path

The Layered Testbench

Five layers, swap-point reuse, and the flat testbench it replaces.

Required

The Static Harness and Environment

Clock, reset, interface, DUT, virtual-interface handoff, and environment wiring.

Required

Tests as Classes

Base and derived tests, plusarg selection, and the end-of-test contract.

Required

Complete Mini Testbench

Every layer working together against a small register file.

Recommended

Path tells you how to spend your time. Required is the core first pass for building a layered testbench. Recommended is what most learners should read. Optional is reference, specialist or revision material that you can return to later.

PacketFIFO step: the three short lessons here (layers, harness, tests) are the plan for the PacketFIFO bench you finish in PacketFIFO Step: A Monitor and Scoreboard. Each one ends with a small PacketFIFO box: its five layers, its interface and harness, and its test classes.

Check yourself Where do the static module world and the dynamic class world meet?

At the virtual interface boundary. tb_top owns one physical interface instance, and every class holds a virtual handle to it. Nothing else crosses between the two worlds.

Be able to whiteboard the five layers and name one swap point per boundary.

  • Retargeting data width touches the interface parameter, the transaction typedef, and the DUT widths as one set.

  • Replaying a failing stream swaps the generator while driver, monitor, and scoreboard stay unchanged.

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See also

  • Stimulus: Generators, Transactions & Drivers
  • Monitors, Scoreboards & Reference Models
  • Self-Checking Tests & Regression