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Course contents

  • Start Here5
  • SystemVerilog Language Foundations28
  • Object-Oriented SystemVerilog for Verification30
  • Constraint Randomization — Interview-Critical Deep Dive39
  • SystemVerilog Assertions — Interview-Critical Deep Dive41
    • SVA Fundamentals
    • Sequences: Temporal Building Blocks
    • Implication and Property Operators
      • |-> vs |=>
      • Vacuous Success
      • Property Operators: not, and, or, if/else, implies
      • nexttime, always, s_eventually, until
      • Designing Good Antecedents
    • Sampled Value Functions
    • Protocol Assertion Cookbook
    • Advanced SVA: Local Variables, Multiclock & More
    • Assertion Debug & Methodology
    • SVA Interview Drills
  • Functional Coverage in SystemVerilog25
  • Testbench Architecture in SystemVerilog24
  • Advanced Language & Integration26
  • Senior & Interview Preparation23
  • Principal-Level Verification34
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←SystemVerilog Assertions — Interview-Critical Deep Dive
  1. Topics
  2. SystemVerilog
  3. SystemVerilog Assertions — Interview-Critical Deep Dive
  4. Implication and Property Operators

Part 4 of 9Part 4 of 9/Assertions (SVA)Intermediate

Implication and Property Operators

How SVA implication, vacuity, property operators, temporal strength, and antecedent design work.

  • 5topics
  • 5lessons

Sequences describe patterns, and properties state obligations about them. The workhorse is implication: when the antecedent sequence matches, the consequent must hold.

Piece

Role

Example

Antecedent

Sequence trigger; each match starts an obligation

req, $rose(req), (req ##1 ack)

Implication

Binds trigger to obligation, same or next cycle

ante |-> cons, ante |=> cons

Property operators

Combine verdicts from the same start tick

not p, p and q, p implies q

Temporal operators

Extend obligations over time, weak or strong

always p, s_eventually p, p until q

Lesson

What it covers

Path

Overlapped vs nonoverlapped

Same-cycle vs next-cycle consequent start, one stimulus with opposite verdicts, and the desugared delay form.

Required

Vacuous Success

Passing assertions that check nothing, and the assert-plus-cover discipline that proves antecedents fired.

Required

Property Operators

Layer rules for not, and, or, if/else, iff, and implies, plus the negation-over-threads trap.

Recommended

Temporal operators

Strong and weak families, until timing to the tick, and safety versus liveness in simulation.

Optional

Designing Good Antecedents

Edge-anchored triggers, qualifier placement, reusable clockless properties, and a review checklist.

Recommended

Required lessons are the core first pass for writing working assertions. Recommended lessons are worth reading for most learners once the first pass works. Optional lessons are reference, specialist material or revision, and you can come back to them when a project needs them.

Check yourself Every assertion in a regression passes, yet a broken grant is never caught. What is checked first?

Whether the antecedents ever fired. A passing implication whose antecedent never matched is vacuous, so each assert needs a paired cover of its antecedent, with cover hits required at sign-off.

Common whiteboard tasks: draw one stimulus with opposite |-> and |=> verdicts, explain a green-but-vacuous assertion, and place the until vs until_with boundary on a tick diagram. Each answer is given in attempts and ticks.

PreviousNext: |-> vs |=>

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Up next|-> vs |=>

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See also

  • SVA Fundamentals
  • Sequences: Temporal Building Blocks
  • Sampled Value Functions