Course map
- 36 lessons
Starts with Algebra Before Gates
- 25 lessons
Starts with Propagation Delay and Levels of Logic
- 27 lessons
Starts with Edge-Triggered State Elements
- 27 lessons
Starts with Split Design: Intent First
- 39 lessons
Starts with Where RTL Meets STA
- 34 lessons
Starts with Reset Is a System Contract
- 57 lessons
Starts with Inference Starts from Coding Style
- 28 lessons
Starts with Parameters vs localparams
- 76 lessons
Starts with Clock gating done right
- 1 lesson
Starts with Glossary and Notation
About this course
Choose a learning path
Pick a path. Each one orders the same lessons for a different goal. Your progress counts on every path.
New terms or suffixes such as _q and rst_n? Keep the Glossary and notation page open beside the lessons.
New to the chip flow, or to simulators, Git and Make? Start with Start Here: RTL and Verification first, then come back here.
New to RTL, or returning after time away.
8 steps · 114 lessons
- RTL Foundations
- Combinational Design
- Sequential Design
- Controller and Datapath
- Moore vs Mealy
- STA Foundations
- Setup, Hold and Slack
- Reset Architecture
At the end you can: read small synchronous designs, write the basic templates from memory, and explain what limits their clock.
Who this course is for
This is a complete RTL design curriculum from first principles through senior/staff-level topics. Each lesson includes extended theory, ASCII diagrams, multiple Verilog examples, waveform guides, interview angles, and hands-on exercises.
Students and new grads entering VLSI/RTL roles
Engineers moving from verification or firmware into design
Interview prep for RTL/design positions (2–10 YOE)
Anyone replacing ad-hoc notes with a structured reference
Start here: 12 lessons for beginners
New to RTL? These twelve lessons are a first introduction, not the full beginner curriculum. Read them in order to meet the main ideas, then follow the Beginner path below for the complete sequence and practice. Each entry says what it teaches.
Algebra Before Gates – Boolean algebra rules that simplify logic before it becomes gates.
Truth Tables as a Debug Anchor – using truth tables to pin down what a block should do when debugging.
Two's Complement Intuition – how negative numbers are represented and why the encoding works.
Modules and Ports – how a Verilog module declares its interface and connects to other blocks.
assign vs always – when a continuous assignment fits and when a procedural block fits.
The Two Process Templates – the two standard always-block shapes for combinational and sequential logic.
Blocking vs Non-blocking – why
=and<=behave differently and how to avoid races.always_ff and always_comb – how SystemVerilog keywords state design intent for synthesis and simulation.
Why Accidental Latches Happen – which coding gaps infer latches and how to close them.
Synchronous Reset and Register Enable – how registers reset and when they update.
Two-Process FSM Style – the recommended two-process structure for controllers.
Minimal but Robust Testbench Structure – a small testbench shape that checks a design automatically.
Course scale
The course is organised into sections, topics and focused lessons, with theory, code, diagrams, review questions, and sign-off guidance.
Structure
Show how the course is organised
rtl/ course hub
rtl/<section>/ section hub (9 parts)
rtl/<section>/<topic>/ topic hub
rtl/<section>/<topic>/<sub>/ focused lessonLesson patterns
Worked examples and waveforms
Corner cases and stress tests
Integration and sign-off notes
Interview categories include advanced scenario + whiteboard drills
Learning paths
The three paths at the top of this page (Beginner, Interview and Senior RTL) list their steps in order, with reading time and, when you are signed in, your progress on each step.
What you will build
Things you build along the way, and the existing lessons where you build or see each one:
Build item | Where you build or see it |
|---|---|
Counters and timers | |
UART transmitter | |
Controller + datapath (GCD) | |
Valid-ready pipeline | |
Synchronous FIFO | |
AXI-Lite register block | |
Asynchronous FIFO | |
Final capstone |
Interview prep vs project work
How each section pays off in interviews and in day-to-day project work:
Section | Common in interviews | Matters most in project work |
|---|---|---|
Foundations | Boolean algebra, blocking vs non-blocking | Widths, signedness and testbench habits |
Combinational | Muxes, adders, latch causes | Latch-free coding and datapath area |
Sequential | Counters, pipelines, skid buffers | Reset values, enables and stall handling |
FSM | Sequence detectors, UART, GCD | Illegal states and outputs on idle cycles |
Timing | Slack math, skew, exceptions | Depth budgets and constraint discipline |
Reset & CDC | Synchronisers, async FIFO, pulses | Reset trees and hostile verification |
Memory & buses | FIFOs, AXI-Lite, address maps | Backpressure, CSR semantics and integration |
Advanced | Parameters, lint rules, assertions | Reuse, waivers and proof scope |
Senior | Trade-offs with evidence, ECO choice | Closure, handoff and debug discipline |
How to study
Follow these steps for each lesson, in the order your chosen path gives:
Read the core lesson first
Run or inspect the code example in simulation — reading is not enough
Answer the check-yourself questions before moving on
Review the interview angle for the lesson
Move on when you can explain the idea and write the pattern from memory
Estimated time: about 40 hours to read through the course, 80-120 hours if you also run every example and work the exercises.