The question

Every combinational operator has a cell waiting for it. Addition becomes an adder, comparison becomes a comparator, a shift becomes a shifter, a ternary becomes a multiplexer, and a case becomes a parallel mux with decoders. Elaboration works one operator at a time and never looks at the neighbours, so the word-level netlist reads like the RTL with one cell per operation. A later pass, techmap, expands each word cell into single-bit generic cells, which is the level the mapper consumes; area and delay estimates begin only after mapping.

The design below exercises five operators over 4-bit buses in a single module: + on two 4-bit buses, == on the same pair, a variable << shift, a ?: select, and a four-way case with a default. One script runs proc and opt_clean, records the word cells, then runs techmap and records the bit cells. Predict first, then read the recorded lists against your guess.

One file, five operators

The script reads the module on its own, selects it as top, and runs proc, which turns processes into word cells, plus opt_clean, which drops unused wires without merging operators. It records stat and the JSON netlist, then asserts the five expected families and the absence of latches: the case has a default, so every path assigns the output. Then techmap runs, the bit-level stat and netlist are recorded, and one PASS line covers both levels, so a passing run certifies the word reading and the bit reading together.

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read_verilog <<EOV
module operators (
  input wire [3:0] a, b,
  input wire [2:0] sh,
  input wire sel,
  input wire [1:0] op,
  output wire [4:0] sum,
  output wire eq,
  output wire [3:0] shl,
  output wire [3:0] m,
  output wire [3:0] c
);
  assign sum = a + b;
  assign eq = (a == b);
  assign shl = a << sh;
  assign m = sel ? a : b;
  always @* begin
    case (op)
      2'd0: c = a;
      2'd1: c = b;
      2'd2: c = a ^ b;
      default: c = 4'd0;
    endcase
  end
endmodule
EOV
hierarchy -check -top operators
proc
opt_clean
tee -o stat_word.txt stat
write_json net_word.json
select -assert-none t:$dlatch
select -assert-count 1 t:$add
select -assert-count 1 t:$shl
select -assert-count 1 t:$mux
select -assert-count 1 t:$pmux
select -assert-min 1 t:$eq
techmap
tee -o stat_bits.txt stat
write_json net_bits.json
select -assert-min 1 t:$_AND_
select -assert-min 1 t:$_MUX_
log PASS: operators infer word cells and then bit cells

What the run recorded

The table below reads the word-level netlist cell by cell; every entry is a recorded count, not a guess from the RTL. Notice the comparator row: only one $eq compares the two buses, and the other two decode the four-valued case selector beside the $pmux. Elaboration does not share decoders between unrelated operators; each operation brings its own.

The full word list is 1 $add, 3 $eq, 1 $logic_not, 1 $pmux, 1 $shl, 1 $mux, 1 $xor: the table rows plus 1 $xor cell for the exclusive-or branch and 1 $logic_not cell finishing the case decode. Nothing here is shared, folded, or simplified; that happens later, in optimization passes that have the whole netlist in view.

From words to bits

Techmap replaces every word cell with single-bit generic cells, and the recorded bit list is 28 $_XOR_, 27 $_OR_, 29 $_AND_, 9 $_NOT_, 25 $_MUX_: 118 cells in total. The adder dominates the count because addition carries across all five sum bits, while the selects become trees of bit muxes. This is the level the mapper works at, so when a later lesson quotes gates or area, this expansion is what those numbers count.

Break it: drop the default

Delete the default line from the case twin and elaborate it with proc alone. The word netlist keeps its select core and gains 1 $dlatch cell holding the old byte whenever the selector parks on the uncovered value. The script below records both halves of that contrast under one PASS line: the full twin asserts no latch with select logic present, and the default-free twin elaborated with proc asserts the latch.

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read_verilog <<EOV
module case_full (
  input wire [1:0] sel,
  input wire [7:0] a,
  input wire [7:0] b,
  input wire [7:0] c,
  input wire [7:0] d,
  output reg [7:0] y
);
  always @* begin
    case (sel)
      2'd0: y = a;
      2'd1: y = b;
      2'd2: y = c;
      default: y = d;
    endcase
  end
endmodule
EOV
hierarchy -check -top case_full
proc
tee -o stat_full.txt stat
write_json net_full.json
select -assert-none t:$dlatch
select -assert-min 1 t:$pmux t:$mux %u
design -reset
read_verilog <<EOV
module case_nodflt (
  input wire [1:0] sel,
  input wire [7:0] a,
  input wire [7:0] b,
  input wire [7:0] c,
  input wire [7:0] d,
  output reg [7:0] y
);
  always @* begin
    case (sel)
      2'd0: y = a;
      2'd1: y = b;
      2'd2: y = c;
    endcase
  end
endmodule
EOV
hierarchy -check -top case_nodflt
proc
tee -o stat_nodflt.txt stat
write_json net_nodflt.json
select -assert-count 1 t:$dlatch
log PASS: full case infers select logic with no latch while the missing branch infers one latch

That is the whole latch lesson in two rows; the latch lesson later in this topic proves the fixes three ways and explains why an always_comb block refuses the second row outright. Read on there for the missing-else shape and the SystemVerilog check.

Common mistakes

Related topics

• Priority Chains versus Parallel Selects

• Reading Netlists and Reports

• Muxes, Decoders and Encoders