The question

An area total is a sum, not a measurement: each cell count times its cell area, added row by row. This lesson builds that sum twice for one 4-bit adder, once against the full teaching library course.lib and once against the restricted nand_only.lib, which offers only INV, BUF and NAND2. Both totals are recordings from the script below, and the comparison shows what a restricted library costs for identical logic.

One adder, two libraries

The script synthesises the adder once, saves the generic netlist, then maps the same gates twice: first against course.lib, then, after reloading the generic design, against nand_only.lib. The assertions pin what each mapping must satisfy: no generic gate survives either run, every mapped netlist holds at least one library cell, and the restricted run additionally holds at least one NAND2 while the wider cells it cannot use never appear.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

read_verilog <<EOV
module adder4(input [3:0] a, b, output [4:0] s);
assign s = a + b;
endmodule
EOV
synth -top adder4 -flatten
design -save generic
tee -o abc_course.txt abc -liberty course.lib -constr typical.constr -D 1000
tee -o stat_course.txt stat -liberty course.lib
write_json net_course.json
select -assert-none t:$add t:$and t:$or t:$xor t:$not t:$mux t:$_AND_ t:$_OR_ t:$_XOR_ t:$_NOT_ t:$_MUX_
select -assert-min 1 t:NAND2 t:NOR2 t:AND2 t:OR2 t:XOR2 t:XNOR2 t:NAND3 t:NOR3 t:AOI21 t:OAI21 t:MUX2 t:INV t:BUF %u
design -load generic
tee -o abc_nand.txt abc -liberty nand_only.lib -constr typical.constr -D 1000
tee -o stat_nand.txt stat -liberty nand_only.lib
write_json net_nand.json
select -assert-none t:$add t:$and t:$or t:$xor t:$not t:$mux t:$_AND_ t:$_OR_ t:$_XOR_ t:$_NOT_ t:$_MUX_ t:AND2 t:OR2 t:XOR2 t:XNOR2 t:NAND3 t:NOR3 t:AOI21 t:OAI21 t:MUX2 t:DFF
select -assert-min 1 t:NAND2
log PASS: adder4 mapped against course.lib and nand_only.lib with both reports recorded

In a commercial flow the library choice is the foundry library plus its operating corner and cell subsets. Here the two teaching libraries play those roles: a full menu against a three-cell diet. The load each output drives is the 50 fF load typical.constr sets, so the only deliberate difference between the runs is the menu the mapper may order from.

The full-library area

Against course.lib the adder maps to 18 cells (AND2 1, AOI21 1, NAND2 5, NOR2 2, OAI21 2, OR2 1, XNOR2 3, XOR2 3) for the full-library total, and ABC's summary agrees on the area at delay 509.54 ps. The chip-area line of the stat report carries the same total, so two passes over one netlist agree.

The XNOR2 and XOR2 rows tie for the largest share at 25.4% each. That pair is the actionable part of the report: if this adder ever needs slimming, the tied covering is where the area sits, and the total alone would never have said so.

Break it: take away the cells

The second run is the deliberate breakage: the same generic gates mapped with only three cells on the menu. The result is 42 cells (INV 18, NAND2 24) for the restricted total, with ABC reporting the same area at delay 922.06 ps. The function never changed; only the covering did. That is the cost of a restricted library, isolated from every other variable because the generic netlist was reloaded unchanged between the runs.

Read the two charts as one story. The full library spreads area across specialised cells, while the restricted run concentrates 72.7% of the restricted total in NAND2. The surcharge buys no extra function; it is the price of rebuilding every cone from NAND2 stages.

What area cannot tell you

An area total counts cell area only. It knows nothing about wire area, which depends on placement and routing that run later, and nothing about power or delay beyond what ABC's accompanying summary reports. A total that looks comfortable here can still fail after routing congestion or under a tighter clock, which is why synthesis area is a budget input rather than a sign-off number.

Common mistakes

Related topics

• Cell counts from stat

• Technology Mapping