Technology mapping turns an optimised Boolean network into real cells. The mapper looks at the network one cone at a time, lists every way to cut each cone into cell-sized pieces, matches library cells against those pieces, and keeps the cover with the best cost. When delay matters more than area on some path, the same machinery picks faster cells there and cheaper ones everywhere else.
This topic rebuilds that flow as five recorded runs. One function maps to a single AOI21 cell until the cell is banned. A cut enumerator proves the k-feasible cuts while a shared DAG shows why tree covering double-counts. A delay sweep trades area for speed on sized cells. Inverter bubbles merge and banned cells are covered without. A 4-bit adder maps to three different libraries, and the areas come from the tool, not from the text.
Read a mapped netlist as a cover: point at any cell and say which subject gates it absorbed.
List the k-feasible cuts of a small cone and explain why a shared node is covered once, not once per parent.
Predict which way area and delay move when a delay target tightens, a load grows, or a cell is banned, and check the prediction in the ABC report.
Explain why the smallest cell loses on a failing path, where inverter bubbles go, and what a dont_use entry costs.
Map one RTL to several libraries in Yosys, prove the generic gates are gone, and read the area trade from stat.
Lesson | What it covers |
|---|---|
Subject graphs, patterns, covers, and a recorded single-cell mapping. | |
k-feasible cuts, a cut enumerator, sharing against double counting, and a shared cell in stat. | |
A recorded delay sweep on sized cells, slack arithmetic, and an area-against-delay chart. | |
Bubble pushing, polarity choice, and a recorded ban with before-and-after netlists. | |
A 4-bit adder on three libraries with recorded areas and a predict check. |
When delay matters more than area on that path: the cheapest cover misses its required time, so the mapper pays extra area for a faster cover. A cell can also lose because it cannot drive its load within the slew limit, or because a dont_use entry bans it. The Area Against Delay lesson shows the first case with recorded numbers.
This hub runs nothing; its flowchart is a drawing of the lesson structure. The evidence for each claim sits on the five lesson pages, each recorded with Yosys 0.69 and ABC and listed in that page's frame.