Part 4 answers: How do I know my RTL actually works?
The design loop is simulate, look, lint and a first synthesis check, repeated until the design and its testbench agree. This part runs that loop on mini_controller: compile and elaborate, simulate, read the waveform in GTKWave, lint with Verilator and ask Yosys what the code really infers.
Along the way it draws the line every RTL engineer must see: simulation-only code versus code that synthesizes into hardware.
What | Detail |
|---|---|
Time | About 2.5 hours, with every example run on your machine. |
You will build | A simulated, linted and synthesis-checked mini_controller, with a waveform you can open. |
You are done when |
|
Run compile, simulate, view and lint on a small design and explain what each stage checks.
Read a waveform and point to the cycle where behavior diverges from intent.
Tell simulation-only code apart from synthesizable code and fix the mix-ups.
# | Lesson | What it covers | Level |
|---|---|---|---|
4.1 | Which stage prints which message. | W | |
4.2 | Run a real simulation, predict it, break it and fix it. | W | |
4.3 | Open the waveform of a failing run and find the bad edge (optional tool). | W | |
4.4 | One line, two warnings, one fix. | W | |
4.5 | Ask Yosys whether your code can become real gates. | W | |
4.6 | Code that simulates versus code that builds hardware. | W |
Lessons are in learning order: each one sets up the problem the next one solves. The glossary and the command cheat sheet are open to you throughout; if something fails, go to the troubleshooting table.
This course stays on the front-end start-up path and links out instead of repeating. These lessons build on or continue what this part teaches.