Choose this route if... | Route | Roughly |
|---|---|---|
You have never written HDL, or never used a shell or Git. | Complete beginner | All 40 lessons, in order |
You write RTL already and want the flow, the loop and the hand-off. | RTL designer | About 22 lessons |
You test or review designs and want the ladder, automation and debugging. | Verification engineer | About 17 lessons |
The parts are in learning order, and reading them in order is the best route if you have the time. Every lesson below is a link, numbered as in its part. The four reference pages (syntax primer, glossary, command cheat sheet and tool versions) belong to every route.
No HDL, Linux or Git. All forty lessons in order, with the exercises and the code. If the first listings look unfamiliar, keep the Syntax Primer open beside Lesson 1.2:
Part 1: How Chips Get Made: 1.1 Idea to Silicon, 1.2 What RTL Is, 1.3 ASIC, FPGA, SoC and IP, 1.4 Front-End and Back-End: Who Does What, 1.5 PPA Primer, 1.6 What Happens After RTL
Part 2: Your Workstation: 2.1 Shell Survival Kit, 2.2 Files, Paths and Layout, 2.3 Git: Save, Compare, Undo, 2.4 Installing and Checking Tools, 2.5 Reading Tool Messages
Part 3: Specify and Architect: 3.1 Writing a Testable Spec, 3.2 From Spec to Microarchitecture, 3.3 Golden Model and Register Contract
Part 4: The Design Loop: 4.1 Compile, Elaborate, Simulate, Synthesize, Lint, 4.2 First Simulation, 4.3 Waveforms with GTKWave, 4.4 Lint with Verilator, 4.5 First Synthesis Check, 4.6 Simulation Code vs Synthesizable Code
Part 5: The Verification Ladder: 5.1 Tests That Can Fail, 5.2 Self-Checking and Golden Model, 5.3 Random Stimulus and Seeds, 5.4 Assertions, 5.5 Coverage, 5.6 Formal in One Lesson
Part 6: Automation and Reproducibility: 6.1 Makefile for the Loop, 6.2 Exit Codes and Pass Markers, 6.3 CI Smoke Test, 6.4 Pinning Tool Versions, 6.5 Smoke vs Nightly
Part 7: Hand-Off to the Back-End: 7.1 What the Back-End Needs, 7.2 Reading a Constraints File, 7.3 The Release Package
Part 8: When Things Go Wrong: 8.1 Troubleshooting Table, 8.2 Debug Habits, 8.3 Beginner Mistakes Checklist
Part 9: Project and Next Steps: 9.1 Project: Spec to Green CI, 9.2 Project Review and Rubric, 9.3 Where to Go Next
Skim Part 1, set up quickly in Part 2, then focus on spec, the design loop, automation and hand-off. This route skips the first four lessons of Part 1 (the chip flow and job roles you probably know), the other Part 5 lessons, and Parts 8 and 9 beyond the project; go back for them when a failure or the project sends you there:
1.5 PPA Primer, 1.6 What Happens After RTL (skim the rest of Part 1)
2.4 Installing and Checking Tools, 2.5 Reading Tool Messages
3.1 Writing a Testable Spec, 3.2 From Spec to Microarchitecture, 3.3 Golden Model and Register Contract
4.1 Compile, Elaborate, Simulate, Synthesize, Lint, 4.2 First Simulation, 4.3 Waveforms with GTKWave, 4.4 Lint with Verilator, 4.5 First Synthesis Check, 4.6 Simulation Code vs Synthesizable Code
6.1 Makefile for the Loop, 6.2 Exit Codes and Pass Markers, 6.3 CI Smoke Test, 6.4 Pinning Tool Versions
7.1 What the Back-End Needs, 7.2 Reading a Constraints File, 7.3 The Release Package
9.1 Project: Spec to Green CI, 9.2 Project Review and Rubric
Spec and the loop first, then the full ladder, with automation and debug habits holding it together. This route leaves out Part 1, most of Part 2 and the hand-off in Part 7; the quick start and lesson 2.4 cover the setup you need:
3.1 Writing a Testable Spec, 3.3 Golden Model and Register Contract
4.2 First Simulation, 4.3 Waveforms with GTKWave, 4.6 Simulation Code vs Synthesizable Code
5.1 Tests That Can Fail, 5.2 Self-Checking and Golden Model, 5.3 Random Stimulus and Seeds, 5.4 Assertions, 5.5 Coverage, 5.6 Formal in One Lesson
6.1 Makefile for the Loop, 6.2 Exit Codes and Pass Markers, 6.3 CI Smoke Test