Part 1 answers: How does an idea become a working chip?
A chip starts as an idea and passes through architecture, RTL design, verification, synthesis, physical design and manufacturing before it runs a program. Each stage hands a precise artifact to the next, and a mistake found late is harder to fix than one found early.
This part walks the whole flow once, names who does what on each side of the front-end/back-end split, and introduces PPA, the performance, power and area trade-off behind many design decisions.
What | Detail |
|---|---|
Time | About 1 hour. Mostly reading; lessons 1.2 and 1.5 each run one small file, and you can leave those until Part 2 has installed the tools. |
You will build | A mental map of the chip flow, and one simulated waveform you can read edge by edge. |
You are done when | You can name the artifact each stage hands to the next and read the eight-edge waveform in lesson 1.2. |
Sketch the full flow from idea to silicon and name what each stage delivers to the next.
Explain what RTL is and where it sits between architecture and gates.
Define performance, power and area, and name the trade-off between them.
# | Lesson | What it covers | Level |
|---|---|---|---|
1.1 | The ten stages from idea to chip, and what goes in and out of each. | F | |
1.2 | Registers, next values and your first waveform. | F | |
1.3 | Four names that answer four different questions. | F | |
1.4 | Who owns what, followed through one unclear sentence. | F | |
1.5 | Performance, power and area, and why 'make it fast' is not a requirement. | F | |
1.6 | Follow one reset from RTL to the tester. | F |
Lessons are in learning order: each one sets up the problem the next one solves. The glossary and the command cheat sheet are open to you throughout; if something fails, go to the troubleshooting table.