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Course contents

  • Quick Start: Your First Green Build
  • How to Use This Course
  • Reading Paths
  • Part 1: How Chips Get Made6
  • Part 2: Your Workstation5
  • Part 3: Specify and Architect3
  • Part 4: The Design Loop6
  • Part 5: The Verification Ladder6
    • Tests That Can Fail
    • Self-Checking and Golden Model
    • Random Stimulus and Seeds
    • Assertions
    • Coverage
    • Formal in One Lesson
  • Part 6: Automation and Reproducibility5
  • Part 7: Hand-Off to the Back-End3
  • Part 8: When Things Go Wrong3
  • Part 9: Project and Next Steps3
  • Reference4
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←Start Here: RTL and Verification
  1. Topics
  2. Start Here: RTL and Verification
  3. Part 5: The Verification Ladder
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    Part 5 of 9Part 5 of 9/The Verification LadderAll levels

    Part 5: The Verification Ladder

    How do I gain confidence the design is right, not just lucky? Write a self-checking test with a reference model that fails on every real-bug mutant.

    • 6topics
    • 6lessons

    Part 5 answers: How do I gain confidence the design is right, not just lucky?

    One passing test proves little; confidence comes from a ladder where each rung catches bugs the lower rungs miss. This part climbs from tests that can fail through self-checking, random stimulus, assertions and coverage to a first look at formal methods.

    Every rung is motivated by a real mini_controller bug that the rungs below it let through.

    Plan for this part

    What

    Detail

    Time

    About 2.5 hours.

    You will build

    A self-checking random testbench that catches planted bugs, with assertions and a coverage report.

    You are done when

    Your testbench fails on every bug mutant and the coverage report shows no unexplained holes.

    Start with 5.1 Tests That Can Fail

    Nine planted bugs show why a pass alone proves nothing.

    After this part you can

    • Write a self-checking test with a reference model that fails on every real-bug mutant.

    • Add assertions and coverpoints that catch a bug directed simulation missed.

    • Explain what formal asks that simulation cannot answer.

    Lessons

    #

    Lesson

    What it covers

    Level

    5.1

    Tests That Can Fail

    Nine planted bugs show why a pass alone proves nothing.

    W

    5.2

    Self-Checking and Golden Model

    Build the checker stage by stage against the golden model.

    W

    5.3

    Random Stimulus and Seeds

    Why one seed proves little, and how to replay a failure.

    W

    5.4

    Assertions

    One rule written as a property, and when it fires.

    W

    5.5

    Coverage

    Read the hole list and close it.

    W

    5.6

    Formal in One Lesson

    Orientation only: what formal tools prove and when to ask for one.

    W

    Lessons are in learning order: each one sets up the problem the next one solves. The glossary and the command cheat sheet are open to you throughout; if something fails, go to the troubleshooting table.

    Where other courses go deeper

    This course stays on the front-end start-up path and links out instead of repeating. These lessons build on or continue what this part teaches.

    • RTL: Self-Checking and Observability

    • RTL: SVA for RTL

    • SystemVerilog: Covergroup Basics

    • RTL: What Formal Adds Beyond Simulation

    Related topics

    • Course hub

    • Previous: Part 4 · The Design Loop

    • Next: Part 6 · Automation and Reproducibility

    PreviousNext: Tests That Can Fail

    Up next

    Up nextTests That Can Fail

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    See also

    • Quick Start: Your First Green Build
    • How to Use This Course
    • Reading Paths