pwd

Shows the folder you are in.

If the answer surprises you, move back before running anything.

ls

Lists the files in the folder.

Dotfiles stay hidden unless asked for.

cd <dir>

Moves to another folder.

cd with no argument returns home; check with pwd after.

mkdir -p <dir>

Creates a folder and any missing parents.

Without -p it stops when a parent is missing.

cat <file>

Shows a whole file.

For long files the start scrolls away; read in parts.

grep <pattern> <files>

Searches files for a text pattern.

Quote the pattern so the shell does not expand it.

find <dir> -name <pattern>

Lists files by name under a folder.

Point it at one folder, not the whole disk.

git init

Starts version tracking in a folder.

Run once per project; a second one in a subfolder nests repos.

git status

Shows changed and staged files.

Read it before every commit.

git add <files>

Stages files for the next commit.

Stage the files you changed, not everything.

git commit -m "message"

Saves staged work as one snapshot.

Say what changed and why.

git diff

Shows unstaged changes line by line.

Diff before you add, status after.

git log

Lists past commits.

Long histories scroll; read the top first.

git restore <file>

Undoes changes to a file.

Restore discards work for good; commit first if unsure.

iverilog -g2012 -Wall -s <top> -o <file> <rtl> <tb>

Compiles the RTL and testbench into a simulation file. -g2012 selects SystemVerilog, -Wall enables warnings, -s names the top testbench, -o names the output.

A file without a timescale draws a -Wall warning; the project design carries the directive.

vvp <file>

Runs the compiled simulation and shows the testbench result.

When the testbench hits $fatal, vvp exits 1 and make exits 2.

verilator --lint-only -Wall --top-module <top> <rtl>

Lints the RTL without running it.

A clean lint does not mean the design works; simulation still has to run.

verilator --binary --timing --assert

Builds a simulation binary with timing and assertion checking, used for the assertion testbench.

Icarus cannot run concurrent assertions, so this step uses Verilator.

yosys -Q -T -p '<script>'

Reads the RTL, builds the hierarchy, optimizes, checks and reports. The script runs read_verilog -sv, hierarchy -check -top, proc, opt, check -assert, stat.

Plain check can exit 0 while warnings remain; check -assert turns them into failures.

make all

Runs lint, then sim, then synth.

Stops at the first failing step.

make sim

Compiles with iverilog, runs with vvp, and confirms the marker line.

A failing testbench fails the target; read the log.

make lint

Lints the RTL with Verilator.

Fix lint warnings before simulating.

make synth

Runs the Yosys check script into build/synth.log.

Read the log even when it passes; warnings point at real hardware.

make clean

Removes the build folder.

Run it when stale outputs confuse a rerun.

make check-tools

Prints each tool version; exits 1 when a tool is missing.

Run it first on a new machine, before make all.