Post-Silicon Debug for RISC-V Platforms: Review Checklist

Review checklist

Review Checklist for Post-Silicon Debug for RISC-V Platforms is anchored on First-failure isolation time, reproducibility rate of silicon issues, and escaped-defect trend after debug closure.. Convert observations into mechanism-backed decisions with explicit ownership.

• Workload scope and KPI targets are explicit.

• Environment metadata is locked and reproducible.

• Mechanism classification is evidence-backed.

• Owner and rollback conditions are documented.

• Validation matrix covers correctness, perf, and power.

• Owners signed: post-silicon validation owner, CPU design owner, firmware debug lead, reliability engineering owner, product quality owner.