Register Conventions and Calling Discipline: Interview Drills

PROMPT
You observe Function-call overhead (instructions per call), spill/reload rate, and ABI conformance pass rate in integration tests. on Register Conventions and Calling Discipline. Walk through root cause and release decision.

STRONG ANSWER
1. Defines workload and earliest failing mechanism.
2. Explains mechanism: The RISC-V ABI assigns semantic roles to integer registers (argument, temporary, saved, stack pointer, return address, and global/thread pointers), enabling predictable interoperability across compilers, operating systems, and libraries. Calling convention rules define who preserves which registers, how arguments and return values are passed, and how stack frames are aligned and unwound. This contract is critical for mixed-language builds, interrupt boundaries, and debug tooling: even highly optimized code must preserve observable ABI guarantees. Performance tuning often centers on minimizing spills and call boundaries while still respecting callee-saved obligations and reentrancy constraints. In practice, correctness issues usually emerge at boundaries (handwritten assembly, trap handlers, context switches, and FFI shims), so teams treat ABI adherence as a first-class verification target rather than a documentation-only concern.
3. Requests proving artifact: ABI usage guide with prologue/epilogue templates, register preservation matrix, and boundary-case checklist for ISRs and context switches.
4. Proposes bounded fix + owner + rollback-safe validation.

WEAK ANSWER
Suggests generic optimization ideas without mechanism proof or owner accountability.

RISC-V EVIDENCE MATRIX - Register Conventions and Calling Discipline

+--------------------------+--------------------------------+--------------------------------+---------------------------+
| Evidence                 | Tells you                      | Does not prove                 | Next action               |
+--------------------------+--------------------------------+--------------------------------+---------------------------+
| perf counter timeline    | where regression appears       | exact mechanism causality      | correlate with trace      |
| decode/control dump      | control intent per instruction | pipeline side-effect ordering  | inspect retire semantics  |
| trap + CSR logs          | privilege/fault behavior       | performance bottleneck alone   | pair with CPI buckets     |
| MMU/TLB walk trace       | translation behavior           | full system QoS impact         | test mixed workloads      |
| post-fix trend graph     | movement after fix             | long-term stability            | run stress matrix         |
+--------------------------+--------------------------------+--------------------------------+---------------------------+