PCIe/CXL Deep Dive · All levels

Advanced Error Reporting (AER): Interview Drills

Interview Drills for Advanced Error Reporting (AER).

Interview drills

Interview Drills for Advanced Error Reporting (AER) focuses on Correctable error rate, uncorrectable error escalation time, and AER mask effectiveness. The purpose is to turn memory observations into mechanism-backed actions with explicit owners and release-safe validation.

diagram

PROMPT
You observe Correctable error rate, uncorrectable error escalation time, and AER mask effectiveness on Advanced Error Reporting (AER). Explain root cause and release decision.

STRONG ANSWER
1. Defines failing traffic context and first transition loss.
2. Explains mechanism: AER logs receiver errors, bad TLP/DLLP, and link integrity events with severity classification. Firmware and OS must map AER sources to device quarantine, link retrain, or workload failover policies.
3. Requests proving artifact: AER register dump, error source tree, and escalation timeline
4. Proposes bounded fix + owner + rollback-safe validation.

WEAK ANSWER
Gives generic PCIe tuning ideas without command evidence, owner accountability, or risk controls.

Interview evidence matrix

diagram

PCIe/CXL EVIDENCE MATRIX - Advanced Error Reporting (AER)

+-------------------------------+--------------------------------+--------------------------------+---------------------------+
| Evidence                      | Tells you                      | Does not prove                 | Next action               |
+-------------------------------+--------------------------------+--------------------------------+---------------------------+
| TLP type mix + credit stall counters    | protocol-layer stall cost    | link integrity and replay behavior   | inspect training margins  |
| queue age + class breakdown   | fairness and starvation risk   | command legality details       | parse command timeline    |
| LTSSM timeline + ordered set progression | timing-window pressure         | root cause by itself           | correlate with topology map|
| eye / Vref / skew snapshots   | PHY margin and drift behavior  | controller policy quality      | pair with schedule logs   |
| CE/UE + scrub telemetry       | reliability trajectory         | immediate perf bottleneck only | map to hotspot apcieesses  |
+-------------------------------+--------------------------------+--------------------------------+---------------------------+

PCIe/CXL deep dive

RAS closure maps AER, poison, and surprise-down events to bounded containment and recovery actions.

Concept diagram

diagram

RAS ESCALATION

detect -> classify -> contain -> recover -> validate

Metric graph

diagram

RAS EVENT MIX

correctable trend   ███████
uncorrectable       ██
surprise-down       █

Reports and artifacts

AER register dump
poison injection log
surprise-down timeline
containment action record

Mini case study

Masked correctable errors accumulated until a surprise-down during peak traffic forced unplanned failover.

Debug branches

Separate CE trend from UE containment paths
Validate poison handling end-to-end
Test surprise-down drain and driver recovery

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this PCIe/CXL topic is closed under real traffic?

Key takeaways

Always tie controller and PHY counter shifts to application latency and throughput outcomes.
Lock firmware timing profile, thermal condition, and DIMM state before comparing PCIe/CXL captures.

Common pitfalls

Chasing peak bandwidth while ignoring p99 latency and fairness tails.
Changing timing guardbands without separating SI noise from scheduling issues.
Declaring closure without reliability gates, fault injection, and regression replay.

Interview answer expansion

Strong interview answers for Advanced Error Reporting (AER) start with workload framing and metric framing, then explain mechanism plainly: AER logs receiver errors, bad TLP/DLLP, and link integrity events with severity classification. Firmware and OS must map AER sources to device quarantine, link retrain, or workload failover policies.

Then propose a measurement plan: TLP routing, credit dynamics, turnaround cost, RAS interference, and PHY margin where relevant.

Finally, present one bounded fix plus regression risk. PCIe/CXL interviews reward explicit tradeoff ownership, not generic tuning slogans.

Practice this lesson