PCIe/CXL Deep Dive · All levels
Error Handling and RAS: Tricky Q&A
Senior interview and review questions for Error Handling and RAS.
Section Q&A bank
Use these drills after completing all topics in Error Handling and RAS. Answer with workload context, mechanism proof, artifact, owner, and release decision.
Why distinguish correctable from uncorrectable AER events in production?
diagram
[INT][PCIE-CXL][ERROR-HANDLING-RAS]
Q: Why distinguish correctable from uncorrectable AER events in production?
A:
Correctable errors may be logged and monitored for trend without service impact. Uncorrectable errors often require immediate containment—function reset, link retrain, or workload migration. Misclassification causes either unnecessary downtime or silent risk accumulation.
FOLLOW-UP TRAP: Masking all AER events or treating every CE as fatal.What must happen when a poisoned TLP reaches host memory?
diagram
[INT][PCIE-CXL][ERROR-HANDLING-RAS]
Q: What must happen when a poisoned TLP reaches host memory?
A:
Memory manager marks affected lines/pages poisoned, notifies consumers, and may offline regions. Drivers must not retry blindly; IOMMU and VM layers need coordinated teardown to prevent corrupted data use.
FOLLOW-UP TRAP: Retrying DMA after poison without isolating affected buffers.How does surprise-down differ from controlled link disable?
diagram
[INT][PCIE-CXL][ERROR-HANDLING-RAS]
Q: How does surprise-down differ from controlled link disable?
A:
Surprise-down is asynchronous with potentially corrupted in-flight state; controlled disable drains transactions first. Recovery paths differ: surprise-down often needs function-level reset and driver re-init.
FOLLOW-UP TRAP: Using hot-unplug flows for surprise-down without draining in-flight IO.What is an effective containment boundary for a CXL Type 3 expander fault?
diagram
[INT][PCIE-CXL][ERROR-HANDLING-RAS]
Q: What is an effective containment boundary for a CXL Type 3 expander fault?
A:
Isolate the HDM region and interleave group, migrate workloads off affected capacity, and preserve host stability. Resetting the entire host for a single expander fault is usually excessive if RAS policy is granular enough.
FOLLOW-UP TRAP: Platform-wide reboot as the only RAS response.Q&A drill guide
diagram
WORKLOAD -> PCIe/CXL SYMPTOM -> TIMING/QUEUE METRIC -> ROOT CAUSE -> FIX -> REGRESSIONSketch while answering
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RAS ESCALATION
detect -> classify -> contain -> recover -> validateKey takeaways
Always tie controller and PHY counter shifts to application latency and throughput outcomes.
Lock firmware timing profile, thermal condition, and DIMM state before comparing PCIe/CXL captures.
Common pitfalls
Chasing peak bandwidth while ignoring p99 latency and fairness tails.
Changing timing guardbands without separating SI noise from scheduling issues.
Declaring closure without reliability gates, fault injection, and regression replay.