Fabric-Attached Memory System Design: Worked Example

Worked example

Worked Example for Fabric-Attached Memory System Design focuses on Effective mem bandwidth, tail latency across NUMA nodes, and RAS event rate. The purpose is to turn memory observations into mechanism-backed actions with explicit owners and release-safe validation.

A field regression flags Effective mem bandwidth, tail latency across NUMA nodes, and RAS event rate. Proper triage locks environment tags, compares baseline vs failing traces, isolates first repeated loss transition, and validates one bounded mitigation before release.

This pattern prevents reactive tuning. The goal is to preserve both performance and reliability while avoiding hidden regressions that appear only at corner conditions.

System view

CREDIT FLOW VIEW - Fabric-Attached Memory System Design

VC0 posted credits:     [####------] 4/10 available
VC0 non-posted credits: [######----] 6/10 available
VC0 completion credits: [###-------] 3/10 available

Stall signature:
- posted credit exhaustion -> write TLP backpressure
- completion credit exhaustion -> read latency cliff

Fabric-attached NUMA profile

NUMA DISTANCE

Node0 CPU --10--> local DRAM
Node0 CPU --40--> CXL.mem pool
Node0 CPU --50--> remote CPU DRAM

Page placement dominates realized bandwidth.

1. Capture baseline and failing command traces under fixed metadata.

2. Verify TLP stall mix, credit ledger, and LTSSM recovery events.

3. Collect NUMA distance table, bandwidth/latency profile, and RAS policy doc.

4. Patch one bounded fix with explicit owner signoff.

5. Re-run closure matrix and choose ship/rollback.

PCIe/CXL deep dive

Memory expansion and coherency require HDM windows, ownership discipline, and NUMA-aware software policies.

Concept diagram

COHERENCY + HDM

CPU caches <-> CXL.cache <-> device memory (CXL.mem/HDM)

Metric graph

EXPANSION BOTTLENECK SHARE

remote latency      ██████
ownership retry     ████
interleave skew     ███

Reports and artifacts

• HDM decode table

• ownership transition trace

• NUMA distance profile

• RAS region policy

Mini case study

Fabric-attached memory increased capacity but p99 regressed until page placement respected NUMA distance.

Debug branches

• Map HDM windows and interleave groups

• Run ownership litmus under contention

• Correlate RAS events with region offline policy

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this PCIe/CXL topic is closed under real traffic?

Key takeaways

• Always tie controller and PHY counter shifts to application latency and throughput outcomes.

• Lock firmware timing profile, thermal condition, and DIMM state before comparing PCIe/CXL captures.

Common pitfalls

• Chasing peak bandwidth while ignoring p99 latency and fairness tails.

• Changing timing guardbands without separating SI noise from scheduling issues.

• Declaring closure without reliability gates, fault injection, and regression replay.

Worked-example reasoning

Suppose Effective mem bandwidth, tail latency across NUMA nodes, and RAS event rate regresses on a production workload. A shallow response only tweaks timing or queue weights. A deeper response compares baseline and failing traces, then identifies the first repeated loss mechanism in Fabric-attached memory expands capacity beyond local DIMMs with NUMA-like latency profiles. System design must balance interleave, page placement, migration policies, and error containment across the fabric..

If command waste dominates, inspect row policy and turnaround cadence. If blocked cycles dominate, inspect refresh scheduling and QoS windows. If margin loss dominates, inspect lane shmoo and thermal drift.

Only then choose a bounded fix: mapping update, scheduler policy change, refresh strategy adjustment, firmware retrain rule, PHY calibration, or package/SI correction.