Host-Device Coherency Contracts

What this topic teaches

Host-Device Coherency Contracts turns PCIe/CXL theory into production-grade review decisions. Host CPUs and CXL devices share a coherency domain defined by snoop filters, directories, and invalidation paths. Contracts specify which agent owns lines, how evictions propagate, and when stores become globally visible.

The main objective is to identify where the first loss starts in the memory service path, prove it with reproducible traces, and close with the smallest owner-controlled fix.

Senior PCIe/CXL work is less about isolated register tuning and more about cross-layer causality: traffic shape, TLP legality, credit accounting, LTSSM stability, PHY margin, and field reliability must agree before signoff.

Senior-engineer framing question

When Coherency miss rate, snoop stall cycles, and fence-to-visible latency regresses, can you prove whether the first failure is locality collapse, timing-window pressure, scheduler fairness loss, lane-margin drift, or reliability policy overhead?

PCIe/CXL PROTOCOL STACK - Host-Device Coherency Contracts

[Application / Driver]
        |
        v
[Transaction Layer]  TLP headers, routing, ordering, completions
        |
        v
[Data Link Layer]    seq/ack, LCRC, replay buffer
        |
        v
[Physical Layer]     encoding, scrambling, LTSSM, lanes
        |
        v
[Link Partner]

Focus: link physical state changes to service-level latency and bandwidth outcomes
Metric tracked: Coherency miss rate, snoop stall cycles, and fence-to-visible latency

Architecture and timing visuals

Draw the mechanism before tuning knobs. These visuals are optimized for design reviews, bring-up triage, and interview whiteboards.

Coherency domain boundary

COHERENCY DOMAIN

CPU caches <---snoop---> CXL device cache
        |                      |
   memory controller    device backing store

Fence semantics define store visibility timing.

Array hierarchy context

PCIe TOPOLOGY MAP - Host-Device Coherency Contracts

[Root Complex]
    |
    +-- Root Port 0 ---- [Switch] ---- [Endpoint A]
    |                      |
    |                      +---- [Endpoint B]
    +-- Root Port 1 ---- [CXL Type 3 Expander]

BDF routing + bridge windows + HDM decode define reachability.

Command timing context

LTSSM TIMELINE - Host-Device Coherency Contracts

time --->  t0      t1       t2        t3       t4
state      Detect  Polling  Config    L0       Recovery
ordered    -       TS1      TS2       TLP/DLLP TS1/TS2
service    down    train    align     active   retrain

Key checks:
- Detect -> Polling timeout
- Config completion before L0
- Recovery trigger correlation with errors

Controller queue context

CREDIT FLOW VIEW - Host-Device Coherency Contracts

VC0 posted credits:     [####------] 4/10 available
VC0 non-posted credits: [######----] 6/10 available
VC0 completion credits: [###-------] 3/10 available

Stall signature:
- posted credit exhaustion -> write TLP backpressure
- completion credit exhaustion -> read latency cliff

Ownership layers

OWNERSHIP LAYERS - Host-Device Coherency Contracts

layer              owner
-----------------  ----------------
protocol/RTL       coherency owner
PHY/SI             PHY + SI/PI owner
firmware/OS        FW + driver owner
validation         compliance + post-silicon

Evidence to collect before changing knobs

Fast closure comes from complete evidence packets, not from isolated counter wins. Every recommendation should carry a metric, artifact, owner, and rollback-safe validation plan.

• Primary metric: Coherency miss rate, snoop stall cycles, and fence-to-visible latency.

• Primary artifact: Coherency contract doc, snoop latency histogram, and fence benchmark.

• Owners to include: coherency owner, CXL architect, software architect, validation owner.

• One reproducible failing traffic slice plus one stable comparator capture.

• One command legality timeline that isolates first failing transition.

• One margin or reliability packet when PHY or RAS behavior is implicated.

Bandwidth-latency operating lens

BANDWIDTH/LATENCY CURVE - Host-Device Coherency Contracts

throughput
    ^
    |     ****  (peak Gen5 x16)
    |   **    **
    |  *        *  <- tail latency inflation
    +----------------> offered load

Metric: Coherency miss rate, snoop stall cycles, and fence-to-visible latency

Root-cause decision tree

ROOT CAUSE TREE - Host-Device Coherency Contracts

symptom: Coherency miss rate, snoop stall cycles, and fence-to-visible latency
  |-- LTSSM / PHY margin
  |-- credit / ordering stall
  |-- coherency / HDM config
  |-- RAS / poison handling
  |-- enumeration / resource conflict

Key takeaways

• Prove first failing transition before touching broad tuning policies.

• Tie command-level behavior to application-visible QoS outcomes.

• Close with accountable owner, rollback criteria, and corner validation.

Common pitfalls

• Optimizing average GB/s while p99 latency and fairness degrade.

• Comparing traces without fixed firmware, timing profile, and thermal tags.

• Declaring closure without reliability and retrain robustness checks.

PCIe/CXL deep dive

Memory expansion and coherency require HDM windows, ownership discipline, and NUMA-aware software policies.

Concept diagram

COHERENCY + HDM

CPU caches <-> CXL.cache <-> device memory (CXL.mem/HDM)

Metric graph

EXPANSION BOTTLENECK SHARE

remote latency      ██████
ownership retry     ████
interleave skew     ███

Reports and artifacts

• HDM decode table

• ownership transition trace

• NUMA distance profile

• RAS region policy

Mini case study

Fabric-attached memory increased capacity but p99 regressed until page placement respected NUMA distance.

Debug branches

• Map HDM windows and interleave groups

• Run ownership litmus under contention

• Correlate RAS events with region offline policy

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this PCIe/CXL topic is closed under real traffic?

Key takeaways

• Always tie controller and PHY counter shifts to application latency and throughput outcomes.

• Lock firmware timing profile, thermal condition, and DIMM state before comparing PCIe/CXL captures.

Common pitfalls

• Chasing peak bandwidth while ignoring p99 latency and fairness tails.

• Changing timing guardbands without separating SI noise from scheduling issues.

• Declaring closure without reliability gates, fault injection, and regression replay.