Fabric-Attached Memory System Design: Reports and Metrics

Reports and metrics

Reports and Metrics for Fabric-Attached Memory System Design focuses on Effective mem bandwidth, tail latency across NUMA nodes, and RAS event rate. The purpose is to turn memory observations into mechanism-backed actions with explicit owners and release-safe validation.

Reports should explain why Effective mem bandwidth, tail latency across NUMA nodes, and RAS event rate moved, not simply that it moved. Require evidence that links the movement to command behavior, queue policy, PHY margin, or reliability controls.

Before/after trend

BEFORE/AFTER TREND - Fabric-Attached Memory System Design

metric        before    after fix
------------  --------  ---------
bandwidth     42 GB/s   48 GB/s
p99 latency   18 us     9 us
error rate    12/hr     0/hr

Evidence matrix

PCIe/CXL EVIDENCE MATRIX - Fabric-Attached Memory System Design

+-------------------------------+--------------------------------+--------------------------------+---------------------------+
| Evidence                      | Tells you                      | Does not prove                 | Next action               |
+-------------------------------+--------------------------------+--------------------------------+---------------------------+
| TLP type mix + credit stall counters    | protocol-layer stall cost    | link integrity and replay behavior   | inspect training margins  |
| queue age + class breakdown   | fairness and starvation risk   | command legality details       | parse command timeline    |
| LTSSM timeline + ordered set progression | timing-window pressure         | root cause by itself           | correlate with topology map|
| eye / Vref / skew snapshots   | PHY margin and drift behavior  | controller policy quality      | pair with schedule logs   |
| CE/UE + scrub telemetry       | reliability trajectory         | immediate perf bottleneck only | map to hotspot apcieesses  |
+-------------------------------+--------------------------------+--------------------------------+---------------------------+

• Track p50/p95/p99 latency and effective bandwidth together.

• Include command and queue context alongside high-level counters.

• Tag reports with firmware, timing profile, and thermal state.

• Call out contradictory evidence instead of hiding it.

PCIe/CXL deep dive

Memory expansion and coherency require HDM windows, ownership discipline, and NUMA-aware software policies.

Concept diagram

COHERENCY + HDM

CPU caches <-> CXL.cache <-> device memory (CXL.mem/HDM)

Metric graph

EXPANSION BOTTLENECK SHARE

remote latency      ██████
ownership retry     ████
interleave skew     ███

Reports and artifacts

• HDM decode table

• ownership transition trace

• NUMA distance profile

• RAS region policy

Mini case study

Fabric-attached memory increased capacity but p99 regressed until page placement respected NUMA distance.

Debug branches

• Map HDM windows and interleave groups

• Run ownership litmus under contention

• Correlate RAS events with region offline policy

Senior review question

Ask: which latency, bandwidth, and reliability evidence proves this PCIe/CXL topic is closed under real traffic?

Key takeaways

• Always tie controller and PHY counter shifts to application latency and throughput outcomes.

• Lock firmware timing profile, thermal condition, and DIMM state before comparing PCIe/CXL captures.

Common pitfalls

• Chasing peak bandwidth while ignoring p99 latency and fairness tails.

• Changing timing guardbands without separating SI noise from scheduling issues.

• Declaring closure without reliability gates, fault injection, and regression replay.

Report interpretation

Fabric-attached memory expands capacity beyond local DIMMs with NUMA-like latency profiles. System design must balance interleave, page placement, migration policies, and error containment across the fabric. PCIe/CXL inefficiency is multiplicative: one extra ACTIVATE, one unnecessary turnaround, one weak lane margin, or one refresh collision repeated across billions of accesses can dominate product tail latency and power.

Use Effective mem bandwidth, tail latency across NUMA nodes, and RAS event rate as the opening signal, not the conclusion. A metric move only becomes actionable when paired with workload context, command traces, training telemetry, and evidence artifacts such as NUMA distance table, bandwidth/latency profile, and RAS policy doc.

Host-device coherency and HDM windows define how expanded memory behaves like first-class system memory. Senior review quality comes from proving a complete chain: request pattern -> memory-state transition -> bottleneck mechanism -> smallest owner fix -> regression-safe validation.

For Fabric-Attached Memory System Design, reports should explain why Effective mem bandwidth, tail latency across NUMA nodes, and RAS event rate moved: fewer row misses, lower turnaround waste, better refresh placement, or stronger lane margin stability.

Strong reports include consistency checks: scheduler narrative matches command logs; PHY narrative matches margin sweeps; reliability narrative matches CE/UE trajectories.