Retiming repositions registers without adding or removing any along a path. Each input-to-output path crosses the same number of registers before and after; only the split of logic between consecutive registers changes, and that split sets the clock period.
Reset-cycle outputs and the power-up flush can still change even when the steady stream does not, so they must be rechecked. Pipelining adds registers to split long paths, which adds latency: the price retiming never pays.
Lesson | What it covers |
|---|---|
Forward and backward register moves across gates and fanout, with a tool-recorded 3-to-2 move. | |
Why latency stays fixed while throughput rises, and when the register count changes. | |
Reset-cycle differences after a move and what equivalence can still show. | |
Cutting a datapath into three stages with valid bits, timed per stage and proved at the right latency. | |
Where retiming sits in a synthesis flow, what blocks a move, and what verification must do instead. |
The clock period changed from 8 ns to 6 ns. Latency did not: each input-to-output path still crosses one register, so each result still takes one cycle.
This hub runs nothing; its flowchart is a drawing of the lesson structure. The evidence for each claim sits on the five lesson pages, each recorded with Yosys 0.70 and ABC and listed in that page's frame.