Every clocked bit in a design lives in one of four flop families: plain, enabled, synchronous reset, or asynchronous reset. Each RTL idiom infers its own generic cell, and the library decides whether that cell maps to a dedicated flop or to a plain flop plus glue logic. This topic runs all four families through inference and mapping against the teaching library, prices each one from the recorded stat reports, and shows where the reset and enable costs really sit.
The headline result to carry through the topic: in this library a synchronous reset is a plain DFF with gates on D, while an asynchronous reset is a dedicated DFFR cell, and the two 10-bit registers report the same total chip area. The cost moves between the flop cell and the surrounding logic instead of changing the sum, which is why this topic always quotes the stat chip area and never the ABC summary line when flops are involved.
Name the generic cell for any plain, enabled, sync-reset, or async-reset block, and prove it with a select assertion.
Read a mapped register as library cells plus glue, and explain which seat the reset or enable cost sits in.
Quote register area from the stat chip total, and say why the ABC summary line misprices any design with flops.
Decide which flops may skip reset, what an initial value guarantees, and what reading too early shows in simulation.
Predict what the legalize-then-exchange flow builds when the library has no matching flop, and what a combined reset-plus-enable costs.
Lesson | What it covers |
|---|---|
The plain clocked block, one flop per bit, width scaling, and the chained-blocking break-it. | |
$dffe becomes DFF plus feedback mux here, and the real clock-power saving comes from a gate. | |
$sdff against $adff with equal mapped totals, plus recovery, removal, and a safe release. | |
Which flops may skip reset, what init records, and what early reads show in simulation. | |
From generic cells to DFF and DFFR via dfflegalize and dfflibmap, plus the no-match fallback. |
q only when en is high and has no reset. Which generic cell does it infer?An enabled flop without reset: $dffe. The enable selects between the new data and the held value, which the next lesson records as a DFF plus feedback mux in this library.
The hub runs nothing; its flowchart is a drawing of the lesson structure. The evidence for each claim sits on the five lesson pages, each recorded with Yosys 0.70 and ABC and listed in that page's frame.