Every lesson in this topic works on one machine: a five-state serial packet receiver. It idles until a start bit arrives, collects a header byte and payload bytes, checks the CRC, and accepts the packet. A synchronous reset returns it to IDLE from any state. States are IDLE, HDR, PAYLOAD, CRC and DONE, and the diagram below is the intended machine the recordings on every page implement.
The topic follows one question per lesson. Coding styles asks which spellings of this machine the tools accept and what each one costs. State encoding asks how the five states are numbered in bits. Unreachable states asks what happens to the three bit patterns no state uses. Output registering asks where the output logic sits. Yosys FSM passes asks how the tool finds the machine in the first place.
Choice | Options | What it trades |
|---|---|---|
Coding style | One-, two- or three-process | Readability against how cleanly the tool sees the state register. |
State encoding | Binary, one-hot or gray | Flop count against decode depth and switching activity. |
Recovery | Default arc, hold, or full case | Safety against extra next-state logic. |
Outputs | Mealy, Moore, or registered | Response latency against output timing. |
Write the same receiver in one, two and three processes, predict the flop counts, and prove two of the spellings equivalent with a recorded run.
Recode the five states three ways, read state flops, logic area and delay, and total chip area off the recorded reports, and say where one-hot wins and loses.
Count the unreachable codes of a 3-bit register with five used states, price the recovery choice in cells, and state what a missing default does.
Move output logic across a flop boundary, read the before-and-after longest paths, and name the latency the move adds.
Run detect, extract, recode and map on the receiver, quote the detector's own log lines, and explain why a register with an initial value or a folded enable is never marked.
Lesson | What it covers |
|---|---|
One-, two- and three-process forms of the receiver and what each infers. | |
Binary, one-hot and gray with recorded area, speed and switching numbers. | |
Invalid codes, three recovery choices, and the recorded price of each. | |
Mealy and Moore outputs and why registering outputs helps timing. | |
How fsm_detect, fsm_extract and fsm_recode handle the receiver. |
Faults and uninitialised flops can land the machine in an all-zero or multi-hot code no case item covers. Without a default recovery arc it never returns, as the unreachable-states page records.
This hub runs nothing; its diagram is hand-drawn. Each claim is evidenced on the five lesson pages, recorded with Yosys 0.70+post and ABC.