Every RTL array lands in one of two places. A small table with awkward access becomes one flop per bit plus read muxes and write decode. A large table with few ports and a registered read becomes a macro instance: a compiled block the tool connects but never builds from gates. The four lessons below record both sides with Yosys: a flop-array sweep that grows linearly with bits, the port styles that decide which side an array lands on, the byte enables and bypass logic that wrap a macro, and the black-box boundary a compiled macro presents to synthesis.
Question | Flop array | RAM macro |
|---|---|---|
Best size | Small tables, around a kilobit or less | Large tables, thousands of bits and up |
Read style | Sync or async read | Sync read in most compiled macros |
Port count | Many ports stay cheap while the memory is small | One or two ports; more ports cost area fast |
Reset | Per-bit reset is natural | No per-bit reset; reset needs a wrapper |
Flow | Mapped with the logic | Black box with a timing model plus a wrapper |
Lesson | What it covers |
|---|---|
A recorded depth and width sweep, the per-bit slope, and the crossover rule against an assumed macro block. | |
Sync and async reads, one write port against two, and what memory_dff absorbs into a port. | |
Per-byte write masks, read-during-write transparency, and a sat-proved bypass wrapper. | |
Black-box macros in synthesis, wrapper contents, and macro selection from a list. |
Flops. At 256 bits the table sits far below the roughly one-kilobit crossover against the assumed 20000-unit macro block, and a flop array needs no wrapper or timing model.
This hub runs nothing; every figure on it is a drawing that summarizes the lesson structure. The evidence for each claim sits on the four lesson pages, each recorded with the Yosys build used by the course checker (0.70+post series, scripts/tools/run-rtl-testbenches.mjs with COURSE=synth) and listed in that page's frame.