Mapping answers one question: given this network and this library, which cells implement it most cheaply? The network is the subject graph: every gate is a node and every wire is an edge. Each library cell is a pattern with an area in library units, and a cover assigns subject nodes to cells so every cell input sits on a primary input or another cell output; the cover cost is the sum of its cell areas. This lesson records that choice on one function.
The function is f = NOT ((a AND b) OR c). The script synthesises it once, saves the generic gates, then maps the same gates twice against course.lib: once with the whole library, once with AOI21 banned. Both runs use typical.constr with a very loose 100000 ps target, so every ABC report carries its Gates, Area, and Delay line, and both runs write their report, stat histogram, and netlist for the lesson to read back. The select lines assert the result: no generic gate may remain after either mapping, and no AOI21 after the ban.
read_verilog <<EOV
module cover(input a, b, c, output y);
assign y = ~((a & b) | c);
endmodule
EOV
synth -top cover
design -save generic
tee -o abc_full.txt abc -liberty course.lib -constr typical.constr -D 100000
tee -o stat_full.txt stat -liberty course.lib
write_json net_full.json
select -assert-none t:$and t:$or t:$xor t:$xnor t:$mux t:$not
select -assert-none t:$_AND_ t:$_OR_ t:$_XOR_ t:$_XNOR_ t:$_MUX_ t:$_NOT_ t:$_NAND_ t:$_NOR_
check
design -load generic
tee -o abc_noaoi.txt abc -liberty course.lib -dont_use AOI21 -constr typical.constr -D 100000
tee -o stat_noaoi.txt stat -liberty course.lib
write_json net_noaoi.json
select -assert-none t:$and t:$or t:$xor t:$xnor t:$mux t:$not
select -assert-none t:$_AND_ t:$_OR_ t:$_XOR_ t:$_XNOR_ t:$_MUX_ t:$_NOT_ t:$_NAND_ t:$_NOR_
select -assert-none t:AOI21
check
log PASS: one function maps with and without its best cellIn a commercial flow the ban list comes from the vendor or the project: a cell uncharacterised for the corner, or one the block cannot route, is marked dont_use. Yosys spells that as abc -dont_use, which is what the second run uses.
Before reading the tool output, list the covers by hand from the cell areas in course.lib. Those areas are library data: INV 1, NAND2 and NOR2 2 each, AND2, OR2, and AOI21 3 each. Three covers compete for f, and the calc block adds each one.
Cover | Cells | Area (library units) |
|---|---|---|
A | AND2 + NOR2 | 5 |
B | NAND2 + INV + NAND2 + INV | 6 |
C | AOI21 | 3 |
f = NOT ((a AND b) OR c); areas in teaching-library area units
cover A = AND2 (3) + NOR2 (2) = 5
cover B = NAND2 (2) + INV (1) + NAND2 (2) + INV (1) = 6
cover C = AOI21 (3) = 3
cheapest of the three = cover C at 3 area unitsCover C wins on paper: one AOI21 absorbs the AND, the OR, and the inversion together. Cover A splits the same logic across two cells and pays for both; cover B rebuilds it from NAND2 cells and discrete inverters and pays the most. The sketch overlays two covers on the subject graph: small dashed boxes for cover A, one large box for cover C.
Yes. The full-library run maps f to a single AOI21 cell with area 3, and the run with AOI21 banned needs 2 cells (AND2 x1, NOR2 x1) with area 5. Banning the best cell costs 2 extra area units on this function.
Mapping | Cells | Area (library units) | Delay (ps, ABC report) | AOI21 cells |
|---|---|---|---|---|
Full library | 1 | 3 | 114 | 1 |
AOI21 banned | 2 | 5 | 228 | 0 |
The full-library row matches cover C exactly — one AOI21, the cheapest cover available. With cover C on the table, ABC picks it, reaching 114 ps against 228 ps banned. The banned row holds no AOI21 cells, as the ban demands, and the area rises by the gap the table shows.
Cover C places every gate in exactly one cell, but that neatness is a property of trees, where each node feeds exactly one parent. Real networks share results: one node's output can feed two parents. Sharing, splitting, and duplication are all everyday outcomes. Classic tree covering splits the DAG at fanout points: the shared node becomes the root of its own tree, built once, and the split loses any optimisation that crossed it. The alternative is duplication, two cells covering one copy each, and the hand-priced 12 in the next lesson is that duplication case, one AND2 charged twice.
The second run in the script is the break-it: the same generic gates, the same library, minus AOI21, so the whole difference between the two table rows is the ban. The banned histogram reads AND2 x1, NOR2 x1: that fallback is the price of one dont_use entry here — small, because a good fallback exists. Where none exists the mapper pays far more, which is why the Inverters and Banned Cells lesson repeats this experiment with two bans stacked.
The full-library row matches cover C, the single AOI21 and cheapest paper cover; the banned row needs a multi-cell fallback with no AOI21 left. The ban costs the gap between the two Area cells: the cheapest available cover against the cheapest remaining one.
Not valid: every node needs a cell, including inverters, because an unassigned node is logic the netlist does not implement. On a DAG a shared node is covered once with fanout to both parents, or duplicated into two cells, so per-node counting double-charges shared logic.
ABC areas, arrivals, cell counts, and netlist pictures on this page come from one Yosys 0.69 run of the script shown, recorded by the course checker (scripts/tools/run-rtl-testbenches.mjs with COURSE=synth): ABC maps f = ~((a & b) | c) against the teaching library course.lib with the full library and with AOI21 banned, with a 0.05 pF default load. The three paper covers (5, 6, and 3 units) are hand-priced from library areas and labelled so on the page. The library is fictional, so absolute areas are teaching units; the cover choice is the point. The subject-graph sketch is a drawing, not tool output.