Large fanouts slow drivers and break slew and capacitance limits. Synthesis repairs them with buffer trees, gate sizing, cloning and restructuring, trading area for rules that must hold.
Term | Meaning |
|---|---|
Fanout | The number of sinks one driver feeds. Large fanout means large load. |
Slew (transition) | How fast a signal edge rises or falls. Heavy loads stretch edges out. |
Capacitance load | Wire plus pin capacitance the driver must charge. It sets delay and slew. |
Buffer tree | Staged buffers that split one large fanout into small, legal steps. |
Cloning | Duplicating a driver so each copy feeds fewer sinks. |
What you can do after this topic: read the three design rules off a library and a constraint file, predict how delay moves with load, size a buffer tree with ceiling division, tell sizing from cloning from restructuring, and price a fanout repair in area before you ask for it. The worked tree on the buffer-trees page stages 64 sinks at branch 4, in groups of 16, 4 and 1.
Lesson | What it covers |
|---|---|
Library and constraint rules, load units on the shared net, and a recorded load comparison. | |
A linear delay model fitted to the real NAND2 table, checked in Python. | |
Ceiling-division stage counts, a 64-flop shared net, the mapper's recorded repair, and the branch-width optimum. | |
X1/X2/X4 choices from a recorded sweep, hand-priced cloning input load, and restructuring for depth. | |
The measured cost of repair: area against fanout, load and target. |
21 buffers: 16 in the first stage, 4 in the second and 1 in the last. Each stage divides the remaining load by 4.
This hub page runs no tools itself. Its repair loop states the commercial flow; the five lessons below record only the delay- and load-driven part of it, since no run sets a design-rule limit. All runs use Yosys 0.69 and ABC against the teaching library sized.lib and are recorded by the course checker (scripts/tools/run-rtl-testbenches.mjs with COURSE=synth).