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Course contents

  • Logic Synthesis Glossary
  • Logic Synthesis Cheatsheet
  • Synthesis Foundations14
  • Logic Optimisation and Mapping20
    • Boolean Optimisation
    • Technology Mapping
    • Cell Libraries and Liberty
      • What a Library Contains
      • Reading the Teaching Library
      • Delay Tables and Interpolation
      • Flops, Power, and Variants
      • Mapping Against the Library
    • Structuring and Buffering
  • Constraints and Timing15
  • Sequential, FSM and Memory19
  • Datapath Synthesis14
  • Area, Power and Test14
  • Verification, ECO and Handoff15
  • Flows and Debugging15
  • Interview and Judgment11
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←Logic Optimisation and Mapping
  1. Topics
  2. Logic Synthesis
  3. Logic Optimisation and Mapping
  4. Cell Libraries and Liberty

Part 2 of 9Part 2 of 9/Logic Optimisation and MappingIntermediate

Cell Libraries and Liberty

Function, area, timing arcs, and delay tables in the course Liberty library.

  • 5topics
  • 5lessons

Every area and delay number in logic synthesis traces back to library entries. Without reading them, a mapping result looks arbitrary and a cheaper cover looks like luck.

After this lesson you can: name what each library entry tells the mapper, and map each lesson to the skill it builds.

A standard-cell library is the menu the mapper orders from. Every entry lists what the cell computes, what it costs, what load it adds to its driver, and how long it takes under stated slew and load. The mapper never invents a gate. It only trades listed entries against each other, so every area and delay number in this course traces back to entries like the ones on these pages.

The teaching library is small and fictional: fifteen cells in course.lib, one size per cell, with made-up but consistent numbers. A second library, nand_only.lib, holds only INV, BUF, and NAND2 at the same areas. Comparing covers across the two shows what choice costs. A third library, sized.lib, offers most cells in three drive strengths and appears wherever a constraint has to change a netlist.

One recorded pair to carry through the topic, from the mapping lesson's runs: one mux plus one AOI cone covers 2 cells at area 8 against course.lib, and 8 cells at area 13 against nand_only.lib. Same logic, different menu.

Flowchart: function, area and pin capacitance flow into net load and delay tables, then into the mapper cover, which produces the area total and path delay.
How a library entry reaches the result: function and area pick the cover, pin capacitance sums into net load, tables turn slew and load into delay, and the cover sets area and delay.

Lesson

What it covers

What a library contains

One NAND2 entry annotated field by field, plus runs that ban NAND2 and then stack a second ban.

Reading the teaching library

All fifteen cells with the real INV and NAND2 delay tables copied from course.lib.

Delay tables and interpolation

Bilinear lookup on the real NAND2 table, checked by a runnable Python block.

Flops, power, and variants

Setup, hold and clock-to-Q from the real DFF groups, plus sync against async reset mapping.

Mapping against the library

A mux and an AOI cone mapped to course.lib and to nand_only.lib, plus a run that bans only MUX2, with recorded areas.

What you can do after this topic

  1. Read any combinational entry in course.lib: function, area, pin load, arcs, and tables.

  2. Look up a cell delay by input slew and output load, and interpolate inside the table.

  3. Read a flop entry: setup and hold limits plus clock-to-output delay.

  4. Predict what banning a cell does to a cover, and confirm it from a stat report.

  5. Name the library before quoting any area or delay, and convert its pF and ns units.

Check yourself Which two table indexes set a cell delay in the non-linear delay model?

Input slew (index_1, the rows) and output load (index_2, the columns). The table entry at that point gives the delay, as the NAND2 table on the interpolation page shows.

Carry one sentence per lesson: entries set cost and load, the teaching library holds fifteen fictional cells, delay comes from two-index tables read slew-first, flops add setup and hold to the same table shape, and no mapping result means anything without the library that produced it.

  • Function and area pick the cover; pin capacitance sums into the load that indexes every delay table.

  • Delay comes from two-index tables read slew-first; flops add setup, hold, and clock-to-Q in the same shape.

  • No mapping result means anything without the library that produced it.

Rule of thumb: name the library before quoting any area or delay.

How this was checked

Topic hub: no tool run. Numbers quoted here come from the recorded Yosys 0.69 runs on the five lessons, and the flowchart is illustrative.

  • Interview: run a mock interview on this topic

Related topics

  • Up: Logic Optimisation and Mapping

  • Previous: Technology Mapping

  • Next: Structuring and Buffering

PreviousNext: What a Library Contains

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See also

  • Boolean Optimisation
  • Technology Mapping
  • Structuring and Buffering