The question

A tied input looks harmless: one pin strapped to 1, one to 0. But each constant turns its gate into a simpler function, and the simpler function feeds the next gate, which may fold in turn. One tie-off can therefore delete a whole cone of logic, and this lesson measures exactly that on a real run.

Constants arrive from several places: pins strapped on the board, parameters fixed for a build, width masks that keep some bits and kill others, and flops loaded with a constant. The tool treats them all the same way, folding forward until no gate has a constant input left. The script flattens the hierarchy first because opt does not push constants through module ports on its own.

One tied input, three gates gone

The design below computes one bit as y = (a & one) | (b & zero) inside a submodule, with the tie-offs strapped at the top level, alongside a 4-bit bus masked by a constant vector. The constants cross the hierarchy as port values rather than literals, so elaboration keeps the gates and the before picture shows them. The flattened script saves the generic netlist, records a stat report, runs opt, and records the second report. Mapping the folded result with ABC gives the final cover. The two assertions pin the outcome: no generic AND, OR or NOT cell survives.

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read_verilog <<EOV
module constfold_core(input wire a, input wire b, input wire [3:0] d, input wire one, input wire zero, input wire [3:0] mask, output wire y, output wire [3:0] q);
assign y = (a & one) | (b & zero);
assign q = d & mask;
endmodule
module constfold(input wire a, input wire b, input wire [3:0] d, output wire y, output wire [3:0] q);
constfold_core core (.a(a), .b(b), .d(d), .one(1'b1), .zero(1'b0), .mask(4'b1010), .y(y), .q(q));
endmodule
EOV
hierarchy -check -top constfold
proc
flatten
delete t:$scopeinfo
design -save pre
tee -o stat_before.txt stat
write_json net_before.json
design -load pre
opt
opt_clean
check
tee -o stat_after.txt stat
write_json net_opt.json
techmap
tee -o abc_after.txt abc -liberty course.lib -constr typical.constr -D 1000
tee -o stat_mapped.txt stat -liberty course.lib
write_json net_after.json
select -assert-none t:$and t:$or t:$not
check
log PASS: constants fold away leaving wires that map to no cells

Read the table as cause and effect. Before optimisation the recorded netlist holds 3 generic AND cells and 1 generic OR cell: two ANDs plus the OR from the single bit, and one wide AND from the mask. After optimisation no generic cells remain, each fold having replaced a gate with an equal function.

recorded stat before opt
5. Printing statistics.

=== constfold ===

        +----------Local Count, excluding submodules.
        | 
       17 wires
       35 wire bits
       13 public wires
       28 public wire bits
        5 ports
       11 port bits
        4 cells
        3   $and
        1   $or

recorded stat after opt
10. Printing statistics.

=== constfold ===

        +----------Local Count, excluding submodules.
        | 
       13 wires
       28 wire bits
       13 public wires
       28 public wire bits
        5 ports
       11 port bits

hand count for the single bit, from the course.lib cell table (AND2 and OR2 cost 3 units each)
before: 2 AND2 + 1 OR2 = 2 x 3 + 1 x 3 = 9 area units
after: y is the wire a = 0 area units
saving: 9 area units, the whole cone

Wider constants: the mask

The second output applies the same idea four times at once: q = d & mask with the top level driving 4'b1010. Each bit folds independently against its own mask bit. Bit 3 and bit 1 meet a 1 and survive as wires, while bit 2 and bit 0 meet a 0 and become constant drivers. The wide AND in the before picture is the elaborated form of this expression, and it is gone in the after picture for exactly this reason.

Masks like this appear wherever software writes a control register with reserved bits: a constant vector folds lane by lane, so a masked bus costs nothing after optimisation. Parameters behave the same way, which is why changing one re-opens the cone and moves the area.

Constants through a flop

The second script ties a constant to a register instead of a gate: a flop whose data input is always 0. There is no combinational fold to perform, so a different pass does the work. opt_dff deletes the flop cell itself once its data input is constant, provided the flop's initial or reset value is undefined or already equals that constant (a flop initialized to 1 with data tied to 0 is kept, since deleting it would change the reset behaviour), and opt_clean then removes the dangling wires.

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read_verilog <<EOV
module flopconst(input wire clk, output wire q);
reg qq;
always @(posedge clk) qq <= 1'b0;
assign q = qq;
endmodule
EOV
hierarchy -check -top flopconst
proc
write_json net_flop_before.json
tee -o log_dff.txt opt_dff
opt_clean
check
write_json net_flop_after.json
select -assert-none t:$dff
log PASS: flop with constant input becomes a constant driver

recorded opt_dff log: banner plus the action line
5. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 0 on $procdff$2 ($dff) from module flopconst.

The recorded netlists hold 1 flop before the pass and 0 after it: the register is gone and the output is a constant wire. Resets and enables fold the same way whenever they are stuck: a flop that can never change state is not storage, it is a tie-off with a clock pin, and the tool treats it as one.

Break it: leave an input undriven

Now change one thing about the setup: leave the second AND input floating. An undriven input is not a constant; it is a wire with no driver, so it carries no value at all: not 0, not 1, and not even an x the folder could resolve. The third script builds y = a & u with u undriven, runs the same opt, and asserts that the AND gate is still there.

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read_verilog <<EOV
module floatin(input wire a, output wire y);
wire u;
assign y = a & u;
endmodule
EOV
hierarchy -top floatin
proc
opt
write_json net_float.json
select -assert-count 1 t:$and
log PASS: undriven input has no driver so its gate survives optimisation

The recorded break-it netlist keeps 1 AND cell after optimisation: nothing folded, because opt folds only known constants and an undriven wire is not one. Contrast that with the main run, where b and zero folded on a known value. Giving the wire a value takes an explicit step such as opt -undriven or setundef, so drive every input explicitly and never depend on a default you have not read.

Common mistakes

Read the after picture bit by bit before quoting any saving: the 1-bits survive as wires, the 0-bits as constants, and neither shows up in the cell count.

Related topics

• Next: Redundancy removal

• Muxes, decoders and encoders