Every streaming interface in this part speaks one handshake. The source offers a beat with valid, the sink answers with ready, and the beat moves on a clock edge where both are high.
Signal | Driver | Meaning |
|---|---|---|
| Source | The payload is meaningful this cycle. |
| Sink | The sink can take a beat this cycle. |
transfer | Both |
|
Each slot is one clock cycle. The xfer lane is valid && ready: a high slot means a beat moves at the edge that ends it.
Slots 0 to 2: the source offers 0xA1 and holds it while ready is low. Nothing moves.
Slot 3: ready rises and 0xA1 transfers once, although valid was high for four slots.
Slots 4 and 5: ready alone moves nothing; 0xB2 then transfers in the slot it is offered.
4 lessons, about 22 min
One. Only the cycle with both high moves a beat. Count transfers, not levels.
The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.
Rules That Keep Flow Control Safe
A beat moves on the clock edge where valid and ready are both high. The source drives valid and the payload, and the sink drives ready.
Valid must not depend combinationally on ready. While valid is high and ready is low, valid and the payload stay stable.
Throughput is transfer events, not levels: count valid && ready edges.
Rule of thumb: the source offers without waiting for ready, and holds the offer until the edge where ready joins it.
Skid Buffer and Pipeline Stages
Two registers hold at most two beats: an output register and a skid register.
Ready is registered and low whenever both are full, so a push never lands in a full buffer.
A pop that coincides with a push passes the new beat straight to the output with no bubble.
Rule of thumb: register the ready, and give the in-flight beat a second register to land in.
AXI-Style Channels and Backpressure
Each channel has its own valid, ready and transfer event, but shared capacity and transaction dependencies can still throttle another channel.
A registered ready breaks the long combinational ready chain through the interconnect.
Size a FIFO against the round-trip latency of the ready path.
Three Pipeline Stage Styles, Measured
Pass-through: full rate, 9 flops, but ready is combinational and grows by one gate per chained stage.
Plain registered slice: registered ready, 9 flops, but at most one word every two cycles.
Skid buffer: full rate and registered ready for 19 flops; under back-pressure it holds more words, so latency rises.
Rule of thumb: if ready must be registered and the link must run at full rate, you need two data registers.
Mini project: a two-master bus with decoder, default slave and timeout
Practice question: Two-stage valid/ready pipeline: throughput, backpressure and skid buffers
Code lab: AXI stream handshake
Code lab: Skid buffer
Practice question: AXI slave interface with write data buffering
Interview: run a mock interview on this topic