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Course contents

  • RTL Foundations36
  • Combinational Design25
  • Sequential Design27
  • FSM & Control27
    • Controller and Datapath
    • Moore vs Mealy
      • Behavioral Difference
      • Side-by-Side: A Sequence Detector
      • Registered Mealy Outputs
      • Choosing and Verifying
    • State Encoding
    • Multi-Cycle Sequencers
    • UART Transmitter
    • Memory Controller
  • Timing & Clocking39
  • Reset & CDC34
  • Memory & Buses57
  • Advanced RTL28
  • Senior & Interview76
  • Glossary and Notation
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←FSM & Control
  1. Topics
  2. RTL Design
  3. FSM & Control
  4. Moore vs Mealy
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    Part 4 of 9Part 4 of 9/FSM & ControlIntermediate

    Moore vs Mealy

    Moore outputs depend on state only, Mealy outputs on state and inputs.

    • 4topics
    • 4lessons

    Topics in this section

    1. 1Behavioral Difference1 lesson
    2. 2Side-by-Side: A Sequence Detector1 lesson
    3. 3Registered Mealy Outputs1 lesson
    4. 4Choosing and Verifying1 lesson

    Moore outputs depend on the state register alone. Mealy outputs depend on the state and the current inputs.

    Model

    Output depends on

    Typical consequence

    Moore

    The current state only

    No direct input-to-output path; decode can glitch near an edge; sometimes one extra state

    Mealy

    The current state and the current inputs

    Reacts in the same cycle; fewer states; outputs can change when inputs do

    Moore outputs are a function of the state register alone. A Mealy output logic also sees the inputs, shown by the dotted line.

    Lessons in this topic

    4 lessons, about 13 min

    1. 1Behavioral DifferenceYou can predict the output timing of a Moore and a Mealy detector for the same input, and say why they are equivalent in function.3 min
    2. 2Side-by-Side: A Sequence DetectorYou can code the two-ones detector as Mealy and Moore, trace both on the same samples, and count the flip-flops each needs.4 min
    3. 3Registered Mealy OutputsYou can register a Mealy output, state the latency cost, and say what registration does and does not fix.3 min
    4. 4Choosing and VerifyingYou can choose Moore, Mealy or registered outputs for a destination, and write a checklist that verifies the FSM.3 min
    Check yourself Which model can respond to an input in the same clock cycle it arrives?

    Mealy. Its outputs are combinational functions of the inputs, so they change as soon as an input does (before the next edge). A Moore output reacts one clock edge later, when the state has changed.

    “Moore or Mealy?” is asked in almost every digital design screen. The strong answer states the definition, draws the output-timing difference, and says which you would choose and why (see the last lesson).

    Revision sheet

    The whole topic on one page, taken from each lesson's Remember box. Read it before an interview, or print it.

    Behavioral Difference

    • A Mealy output uses the state and the live input, so it responds in the same cycle.

    • A Moore output uses the state only, so it follows the clock edge that enters the state.

    • A Mealy output feeding another block is a combinational path from your input to their logic.

    Side-by-Side: A Sequence Detector

    • Read the output just before the rising edge, where the input is settled and the state has not yet updated.

    • Mealy y = (state == S1) && x; drop the && x and it signals only that the previous sample was 1.

    • Moore needs a state for 'two ones seen', so it costs three states against two.

    Rule of thumb: the Moore output is the Mealy output delayed by one cycle.

    Registered Mealy Outputs

    • Registering moves the decision from before the capture edge to after it.

    • A registered Mealy output is a Moore machine whose state includes the output bit.

    • Choose by the receiver's timing and latency contract. Source registration alone does not handle CDC.

    Choosing and Verifying

    • Boundaries want registered outputs, and local fast paths want Mealy.

    • Reach every state through legal inputs rather than forcing the state register.

    • Check reset state, defaults, reachability, progress under the environment and illegal-state behaviour.

    Practise it

    • Mini project: an SPI master, controller and datapath

    • Practice question: Types of FSMs and their difference

    • Practice question: How outputs are generated in Moore FSMs

    • Code lab: Sequence FSM

    • Practice question: FSM output encoding: registered vs combinational hazards

    • Interview: run a mock interview on this topic

    PreviousNext: Behavioral Difference

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    Up nextBehavioral Difference

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    See also

    • Controller and Datapath
    • State Encoding
    • Multi-Cycle Sequencers