Three process types, three promises

Each process type states what the block implements. The tool then checks that the code keeps the promise.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23

module seq_comb_demo (
  input  logic       clk, rst_n,
  input  logic [1:0] sel,
  input  logic [7:0] a, b, c,
  output logic [7:0] y,
  output logic [7:0] y_q
);
  // Pure logic: every path assigns y, so no latch is possible
  always_comb begin
    y = '0;                           // default
    unique case (sel)
      2'd0: y = a;
      2'd1: y = b;
      2'd2: y = c;
      default: y = '0;
    endcase
  end

  // Registered copy of the result
  always_ff @(posedge clk or negedge rst_n)
    if (!rst_n) y_q <= '0;
    else        y_q <= y;
endmodule

Incomplete assignments infer latches

1
2
3
4
5
6

// bad-example: y is not assigned when en is 0 -> a latch is inferred
module latch_bug (input logic en, a, output logic y);
  always_comb begin
    if (en) y = a;          // no else branch
  end
endmodule

Many tools can warn that y has no value on every path, which implies a latch. Enable the checks and review each report. With a plain always @(*) the language accepts the latch, and lint and synthesis only warn, because nothing said the block was meant to be combinational. With always_comb the same latch contradicts declared intent, so tools can treat it as an error.

The fix is a default assignment or an else branch:

1
2
3
4
5
6

module latch_fixed (input logic en, a, output logic y);
  always_comb begin
    y = 1'b0;               // default makes every path assign y
    if (en) y = a;
  end
endmodule

Unique and priority

These modifiers state how case branches relate. They replace the old full_case parallel_case pragmas. Synthesis tools honoured those pragmas but simulators ignored them, so simulation and hardware could disagree, and a wrong pragma went unnoticed.

• unique case promises exactly one matching branch. Simulation can warn on overlap or no match, so enable the checks and review each report. A default branch suppresses the no-match report, while a pre-case default assignment still leaves it reported. Both can give a deterministic value.

• priority case and priority if describe ordered branches, of which at least one matches. Synthesis can use that assumption to simplify the logic, so keep the promise exact.

Related topics

• Latch inference in depth