What the tool sees

Three codings of the same 64-word RAM. Only the first has the synchronous-read, no-array-reset structure expected by a conventional synchronous block RAM. Actual mapping depends on the target resources and synthesis flow.

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// Good: a plain synchronous single-port RAM
module ram_good #(parameter int AW = 6, DW = 8) (input logic clk, we, input logic [AW-1:0] addr, input logic [DW-1:0] din, output logic [DW-1:0] dout);
  logic [DW-1:0] mem [2**AW];
  always_ff @(posedge clk) begin
    if (we) mem[addr] <= din;
    dout <= mem[addr];
  end
endmodule
// Bad: asynchronous (combinational) read
module ram_async_read #(parameter int AW = 6, DW = 8) (input logic clk, we, input logic [AW-1:0] addr, input logic [DW-1:0] din, output logic [DW-1:0] dout);
  logic [DW-1:0] mem [2**AW];
  always_ff @(posedge clk) if (we) mem[addr] <= din;
  assign dout = mem[addr];
endmodule
// Bad: reset applied to every word of the array
module ram_reset #(parameter int AW = 6, DW = 8) (input logic clk, rst_n, we, input logic [AW-1:0] addr, input logic [DW-1:0] din, output logic [DW-1:0] dout);
  logic [DW-1:0] mem [2**AW];
  always_ff @(posedge clk) begin
    if (!rst_n) for (int i = 0; i < 2**AW; i++) mem[i] <= '0;
    else begin
      if (we) mem[addr] <= din;
      dout <= mem[addr];
    end
  end
endmodule

After reading the source with read_verilog -sv and selecting the module, use proc; memory -nomap; stat; dump to inspect generic memory cells and their port parameters. The -nomap option skips memory_map; a plain memory run includes that pass and lowers any remaining generic memories into word-wide registers and address decoding. A generic memory cell is intermediate inference evidence, not proof of a mapped block RAM. The table describes structural expectations, not measured cell counts:

The ram_reset case is instructive. Its output is functionally registered like ram_good, but dout holds during reset, so Yosys keeps that register as a separate $dff instead of merging it into the read port. The bigger problem is the write side: before port optimization, the loop produces 64 extra reset writes. Optimization may merge ports, but it cannot remove the requirement to clear every stored word in one cycle, which a conventional block RAM cannot implement. For ram_reset, the generic fallback is registers plus a mux tree.

To establish actual block-RAM mapping, run the target-specific synthesis flow and inspect the mapped RAM primitives, dimensions, and read/write behavior. Do not treat a generic memory count or RD_CLK_ENABLE alone as proof that a device RAM resource was selected.

Memory contents are almost never reset; for clean contents, write zeros with a short state machine after reset.

Rules for inference

1. Use a plain array logic [DW-1:0] mem [DEPTH] and index it.

2. Write synchronously, in a clocked always_ff, with a write enable.

3. Read synchronously: assign the read data to a register on the clock edge. This matches the block RAM's registered output.

4. Don't reset the array. Reset the control logic around it.

5. One write per port per cycle. Multiple writes to the array from different branches become extra ports.

6. Keep the address and enable logic simple; wide muxes in front of the array may defeat the mapping.

7. Read the synthesis report: check the tool reports a RAM of the expected size and type, not thousands of flops.

Common mistakes

Related topics

• Single-port RAM template