After reset, every flop that matters has a known value, and every output is defined.
Reset asserts whatever the state of the clocks: at power-up there may be no clock yet.
Reset releases only when each domain's clock is stable, in an order the design can tolerate.
Software and other blocks know how long to wait before using the design.
Asynchronous reset | Synchronous reset | |
|---|---|---|
Code |
|
|
Acts without a clock | Yes | No: needs a clock edge |
Extra logic | None in the data path (flop has a reset pin) | A gate on D for every reset flop |
Release timing problem | Yes: recovery/removal; needs a synchroniser on release | Ordinary D-path setup/hold still apply; use a synchronised and timed reset input |
Reset glitch risk | A glitch on | A glitch is filtered unless it lands on a clock edge |
Typical use | Control/state flops, anything that must start clean with no clock | Datapath where area/timing prefer plain flops |
Each slot is half a clock period (5 ns), so a running clock alternates 0 and 1 and a stopped clock stays flat.
The clock stops low after slot 1 and stays low in slots 2 to 4.
rst_n falls in slot 3, while the clock is stopped. q_async falls in the same slot: no clock edge is needed.
q_sync keeps its 1 until the clock restarts and rises in slot 5, and only then clears.
rst_n is released in slot 6, on a falling edge, and both flops capture d = 1 at the rise in slot 7.
The full code sits under Testbench below.
Synchronous reset syntax is not CDC protection. An asynchronous reset source can violate the reset mux's D-path setup/hold on assertion or release. Synchronise it to this clock and time the resulting path; the falling-edge release in this ideal example deliberately avoids that sampling window.
Asynchronous assert (with a synchronised release): it forces IDLE immediately, without waiting for the clock.
The testbench stops the clock, then checks both reset styles.
`timescale 1ns/1ps
module ff_async (input logic clk, rst_n, d, output logic q);
always_ff @(posedge clk or negedge rst_n)
if (!rst_n) q <= 1'b0;
else q <= d;
endmodule
module ff_sync (input logic clk, rst_n, d, output logic q);
always_ff @(posedge clk)
if (!rst_n) q <= 1'b0;
else q <= d;
endmodule
The test stops the clock before asserting reset. The asynchronous flop clears at once, while the synchronous flop holds its value until the clock restarts.
That difference decides which style suits logic that must be safe during clock start-up.