RISC-V Design · All levels

Hazard Detection Basics in Decode: Theory Deep Dive

Theory Deep Dive for Hazard Detection Basics in Decode.

Theory deep dive

Theory Deep Dive for Hazard Detection Basics in Decode is anchored on RAW stall cycles per kilo-instruction and percentage of avoidable stalls removed by forwarding.. Convert observations into mechanism-backed decisions with explicit ownership.

Theory matters when it predicts engineering outcomes. Tie abstract ISA and microarchitecture concepts to measurable behavior in trace and counter data.

Pipeline model

diagram

RISC-V PIPELINE DIAGRAM - Hazard Detection Basics in Decode

PC -> IF -> ID -> EX -> MEM -> WB
      |     |      |      |      |
  i-cache decode  ALU/BR  LSU    regfile write
              \   |
               +-> branch resolve + redirect

Hot paths:
  - branch + load-use dependencies in ID/EX
  - memory latency stretching MEM stage
  - writeback arbitration for integer/vector units

Focus: keep control hazards predictable

Privilege model

diagram

PRIVILEGE MODE STACK - Hazard Detection Basics in Decode

            +------------------------------+
            | Machine mode (M)             |
            | firmware, PMP, trap root     |
            +---------------+--------------+
                            |
                    delegated traps
                            v
            +------------------------------+
            | Supervisor mode (S)          |
            | kernel, page tables, drivers |
            +---------------+--------------+
                            |
                    ecall / syscall
                            v
            +------------------------------+
            | User mode (U)                |
            | applications, libraries      |
            +------------------------------+

Key rule: each upward transition records cause + PC in trap CSRs.

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