Hazard Detection Basics in Decode: Interview Drills

PROMPT
You observe RAW stall cycles per kilo-instruction and percentage of avoidable stalls removed by forwarding. on Hazard Detection Basics in Decode. Walk through root cause and release decision.

STRONG ANSWER
1. Defines workload and earliest failing mechanism.
2. Explains mechanism: Decode is the first stage that can compare source register indices against destination registers already in flight, so it becomes the anchor point for hazard classification. Basic logic catches read-after-write hazards for operations whose results are not yet available, plus structural conflicts such as a busy multiplier or a blocked memory pipeline. The hazard unit then chooses between stalling decode, inserting bubbles, or allowing issue with forwarding assumptions. Even in simple in-order cores, edge cases matter: x0 dependencies must be ignored, CSR reads and writes can serialize unexpectedly, and load-use latency usually requires a one-cycle interlock unless the data path supports same-cycle bypass. Reliable behavior depends on synchronizing hazard state with flush events so stale dependencies do not survive control redirects.
3. Requests proving artifact: Hazard matrix covering producer-consumer distance, bypass eligibility, and required interlock action for each instruction class.
4. Proposes bounded fix + owner + rollback-safe validation.

WEAK ANSWER
Suggests generic optimization ideas without mechanism proof or owner accountability.

RISC-V EVIDENCE MATRIX - Hazard Detection Basics in Decode

+--------------------------+--------------------------------+--------------------------------+---------------------------+
| Evidence                 | Tells you                      | Does not prove                 | Next action               |
+--------------------------+--------------------------------+--------------------------------+---------------------------+
| perf counter timeline    | where regression appears       | exact mechanism causality      | correlate with trace      |
| decode/control dump      | control intent per instruction | pipeline side-effect ordering  | inspect retire semantics  |
| trap + CSR logs          | privilege/fault behavior       | performance bottleneck alone   | pair with CPI buckets     |
| MMU/TLB walk trace       | translation behavior           | full system QoS impact         | test mixed workloads      |
| post-fix trend graph     | movement after fix             | long-term stability            | run stress matrix         |
+--------------------------+--------------------------------+--------------------------------+---------------------------+